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Commit Graph

1408 Commits

Author SHA1 Message Date
ddcd6065e8 rtio: drive InputCollector.coarse_timestamp 2017-09-19 17:46:38 +08:00
ff8e17ab89 rtio: use input collector module 2017-09-19 15:53:35 +08:00
4dc80e3d05 rtio: add missing import 2017-09-19 15:53:23 +08:00
06a0707c00 rtio: add simulation unit test for input collector 2017-09-19 15:30:44 +08:00
d37577a8a1 rtio: add input collector module 2017-09-19 15:30:30 +08:00
6dc9cad2c9 rtio: add explanation about cri.counter 2017-09-19 12:05:12 +08:00
81d6317053 rtio/sed: take global fine TS width 2017-09-18 11:30:49 +08:00
65baca8c57 rtio: clean up error-prone rtlink.get_or_zero() 2017-09-17 16:11:36 +08:00
0824e0aeae gateware/targets: remove deprecated ofifo_depth parameter 2017-09-16 17:04:11 +08:00
e2c1d4f3d5 rtio/sed: trigger collision error on non-data replace 2017-09-16 17:01:23 +08:00
0e25154e25 rtio/sed: quash writes to LogChannel 2017-09-16 15:19:30 +08:00
1cfe90b1d9 rtio/sed/Gates: fix fine_ts_width computation 2017-09-16 15:09:21 +08:00
30e7765a2e drtio: add missing import 2017-09-16 14:36:27 +08:00
a3bb6c167c rtio: use SED 2017-09-16 14:13:42 +08:00
131f5e4a3b rtio/sed/LaneDistributor: fix CRI address 2017-09-16 14:13:01 +08:00
25c644c663 rtio/sed: add top-level core unit test 2017-09-16 14:05:08 +08:00
a155a481b1 rtio/sed: add top-level core 2017-09-16 14:04:56 +08:00
92c63ce2e4 rtio/sed: rename fifos/gates, refactor tsc 2017-09-16 14:03:48 +08:00
ac52c7c818 rtio/sed/LaneDistributor: style 2017-09-16 14:02:37 +08:00
7b299ba583 rtio/sed: remove obsolete ofifo_depth from test_output_driver 2017-09-16 14:01:19 +08:00
6b7a1893c7 rtio/sed/OutputDriver: support channels with different fine timestamp widths 2017-09-16 10:53:30 +08:00
f39ee7ad62 rtio/sed: fix seqn_width 2017-09-16 10:52:37 +08:00
064503f224 rtio/sed/LaneDistributor: support specifying existing CRI 2017-09-16 10:52:13 +08:00
1cb05f3ed5 rtio/sed/LaneDistributor: persist underflow/sequence error until next write 2017-09-16 10:51:44 +08:00
3c922463a0 style 2017-09-15 15:36:46 +08:00
8e5ab90129 rtio/sed: add FIFO wrapper 2017-09-15 15:36:34 +08:00
490c9815a2 rtio/sed: add TSC/gate (untested) 2017-09-14 19:53:21 +08:00
181cb42ba8 rtio/sed: centralize all layouts in one file 2017-09-14 19:52:31 +08:00
1b61442bc3 rtio/sed: fix lane spreading and enable by default 2017-09-13 22:48:10 +08:00
8cfe2ec53a rtio/sed: fix sequence number width computation 2017-09-13 22:11:41 +08:00
a92a955d1e rtio/sed: use __all__ 2017-09-13 18:17:22 +08:00
feec6298a5 rtio/sed: add lane distributor simulation unittest 2017-09-13 18:00:16 +08:00
c74abccfd5 rtio/sed: lane distributor fixes 2017-09-13 17:50:06 +08:00
bdd96084c5 rtio/sed: add lane distributor (untested) 2017-09-13 00:07:26 +08:00
faf54127ac rtio/sed: remove VCD fine in unittest 2017-09-11 23:07:09 +08:00
a2b7894134 rtio/sed: add output driver simulation unittest 2017-09-11 23:05:10 +08:00
00ff3f5b0d rtio/sed: fix output driver busy output 2017-09-11 23:04:52 +08:00
64d9381c36 rtio/sed: remove uneeded yield in test_sed_output_network 2017-09-11 23:02:56 +08:00
666bc600a2 rtio/sed: add output driver (untested) 2017-09-11 11:10:28 +08:00
1d2ebbe60f rtio/sed: make ON payload layout configurable, add latency function 2017-09-11 09:06:40 +08:00
527b403bb1 rtio/sed: add output network simulation unittest 2017-09-10 23:41:20 +08:00
c5d6a2ba1a rtio/sed: more output network fixes 2017-09-10 23:41:04 +08:00
96505a1cd9 rtio/sed: output network fixes 2017-09-10 23:23:10 +08:00
5646e19dc3 rtio/sed: add output network (untested) 2017-09-10 14:38:43 +08:00
Florent Kermarrec
2091c7696a artiq/gateware/targets/sayma_amc_standalone: fix serwb_pll vco_div and serwb_phy mode 2017-09-06 09:18:12 +02:00
9edff2c520 remote_csr: interpret length as CSR size, not number of bus words 2017-08-31 13:34:48 +08:00
0a5904bbaa firmware: support for multiple JESD DACs 2017-08-31 13:05:48 +08:00
a4144a07c4 sayma_amc: add converter SPI config defines 2017-08-31 13:04:38 +08:00
bacf8a1614 style 2017-08-31 12:52:09 +08:00
ad0a940e2d sayma_rtm: hook up DAC SPI 2017-08-31 11:48:54 +08:00
f765dc50de sayma_rtm: do not keep DACs in reset 2017-08-31 11:44:33 +08:00
a67659338d sayma: clean up serwb comments 2017-08-31 11:42:01 +08:00
Florent Kermarrec
660f9856ec gateware/serwb: add test for phy initialization 2017-08-30 17:59:10 +02:00
Florent Kermarrec
9650233007 gateware/serwb: change serdes clock domain to serwb_serdes 2017-08-30 15:44:44 +02:00
Florent Kermarrec
32ca51faee gateware/targets/sayma_amc_standalone/rtm: use new serwb modules 2017-08-30 15:25:20 +02:00
Florent Kermarrec
41d57d64f6 gateware/serwb: SERWBPLL, SERWBPHY, SERWBCore and add checks in delay finding to verify the sampling window 2017-08-30 14:40:11 +02:00
Florent Kermarrec
9ba50098a8 gateware/test/serwb: use unittest for in test_etherbone 2017-08-29 17:31:01 +02:00
Florent Kermarrec
7d7f6be7ce gateware/serwb: generate wishbone error if link loose ready in the middle of a transaction 2017-08-29 16:41:29 +02:00
Florent Kermarrec
60ad36e7d6 gateware/serwb: generate wishbone error on wishbone slave when access while link is not ready 2017-08-29 13:43:26 +02:00
Florent Kermarrec
89558e2653 gateware/serwb: for the initial version set delay in the center of the valid sampling window and don't use phase detectors
we'll use phase detectors later when it will be working reliably for both artix7 and kintex ultrascale
2017-08-29 13:38:52 +02:00
26a11a296c sayma_rtm: drive DAC control signals 2017-08-26 16:57:02 -07:00
d609c67cbd sayma_rtm: set clock mux pins 2017-08-26 16:48:10 -07:00
9194402ea5 sayma_rtm: expose HMC SPI bus 2017-08-26 16:31:31 -07:00
dbc12540da sayma_amc: register RTM CSR regions from CSV 2017-08-26 14:48:11 -07:00
54c75d3274 sayma_rtm: use CSR infrastructure, generate CSR CSV 2017-08-23 17:19:53 -04:00
668450db26 sayma_amc: add serwb 2017-08-21 18:11:29 -04:00
0459a70cf6 sayma_amc: cleanup, fix RTM UART forwarding 2017-08-21 16:49:42 -04:00
1f2b373d09 sayma_rtm: remove unnecessary serwb_control 2017-08-21 16:37:13 -04:00
bfea297279 targets: add Sayma RTM 2017-08-21 15:58:01 -04:00
53c7f92fdc serwb: add __init__.py and expose submodules 2017-08-21 15:57:43 -04:00
dac3a78b75 serwb: style, use migen, fix imports 2017-08-21 12:35:59 -04:00
Florent Kermarrec
da90a0fa12 Add test for Etherbone
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ec62242659910ad1726beb00ff15b3f0a406615
2017-08-21 12:31:49 -04:00
Florent Kermarrec
44dc76e42e Add serial Wishbone bridge
Files copied directly from https://github.com/enjoy-digital/sayma_test @ 9ce2cba87896d056819dc2edc54f0453a86162c3
2017-08-21 12:22:05 -04:00
d6b624dfbe sayma_amc: connect RTM serial and second serial 2017-08-20 19:01:55 -04:00
bee4902323 add Sayma AMC standalone target 2017-08-20 11:47:45 -04:00
1dab7df846 kc705_sma_spi: fix permissions 2017-08-20 10:54:24 -04:00
df4f38a1e4 kc705: add pullup on SD card MISO 2017-07-24 22:26:16 +08:00
a201a9abd9 drtio: multilink transceiver interface 2017-07-18 13:27:33 +08:00
9045b4cc19 drtio: initial firmware support for multi-link 2017-07-18 00:40:21 +08:00
4deb5f6a45 gateware: use new MiSoC Wishbone address system 2017-07-13 19:16:49 +08:00
mntng
40ca951750 kc705: add SPI bus for memory card
This will be useful for SPI unit tests using a SD card as victim.
2017-07-12 00:27:44 +08:00
7b130a2c32 sawg: confirm smooth(order=3) 2017-07-07 11:36:03 +02:00
2f1029c292 Revert "sawg: advance dds 1/2 by one sample group"
This reverts commit 8e0a1cbdc8.

c.f. #772

The underlying issue is still the same. You will always find something that does not match when trying to compare the DDS with the parallelized DUC. They are just different. I could correct it for phase but then it will fail for amplitude. Or you'll compare the offset channel to phase1 or amplitude1. Let's state that equal things are well synchronized but unequal things may have a deterministic latency difference of strictly less than one coarse RTIO cycle.
2017-07-04 17:55:19 +02:00
8e0a1cbdc8 sawg: advance dds 1/2 by one sample group
closes #772
2017-07-04 16:51:58 +02:00
91ca9fbcad sawg: also give offset some headroom
closes #771
2017-07-04 16:50:06 +02:00
78d1f0fdf6 sawg: fix PhasedAccu resets 2017-07-04 11:56:21 +02:00
Florent Kermarrec
2910b1be5e artiq/gateware/rtio/dma: replace leave_out with omit in Record.connect 2017-07-04 10:48:06 +02:00
838127d914 rtio: break DMA timing path 2017-07-02 10:24:01 +08:00
911ee4a959 rtio: make pipelined logic reset_less
* latency-corrected counters
* registered error logic
2017-06-29 12:55:32 +02:00
600a48ac61 dsp.fir: cleanup 2017-06-29 12:18:48 +02:00
dca662a743 dsp.fir: pipeline final systolic adder 2017-06-29 11:33:19 +02:00
32a33500c8 dsp.fir: actively cull zero delays 2017-06-29 11:24:56 +02:00
f520d4a768 rtio: undo _RelaxedAsyncResetSynchronizer 2017-06-28 22:08:15 +02:00
3cbbcdfe96 sawg: don't enable_replace for Config
closes #762
2017-06-28 20:31:40 +02:00
f2632e0fd1 sawg: adapt latency to fir changes
closes #748
2017-06-28 20:12:30 +02:00
e7db2c6578 dsp.accu: reset_less outputs 2017-06-28 20:04:58 +02:00
6bb994228f dsp.fir: drop x shift 2017-06-28 19:55:15 +02:00
01847271c5 rtio: use reset_less signal for reset fanout 2017-06-28 19:43:55 +02:00
b9859cc0c3 dsp.fir: remove old/wrong comment 2017-06-28 19:21:57 +02:00
55b5b87490 fir: simplify latency compensation
Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
2017-06-28 19:13:43 +02:00
d1e5dd334f sawg: use pipeline reset 2017-06-28 19:09:39 +02:00
6418205906 dsp.fir: use pipelin-reset 2017-06-28 19:09:21 +02:00
07f5e99140 dsp/sat_add: works after previous changes 2017-06-22 18:24:22 +02:00
f78d5a87e9 dsp/test: skip and fix sat_add 2017-06-22 18:01:31 +02:00
47928a2c0d sawg: disable limiter
temporary workaround to permit testing other aspects
2017-06-22 17:31:04 +02:00
cd2ac53bc5 dsp/sat_add: make width mandatory 2017-06-22 17:28:39 +02:00
9b940aa876 dsp/sat_add: spell out logic more 2017-06-22 16:55:13 +02:00
d0cf0f2b87 sawg/limiter: make signed signals explicitly 2017-06-22 13:44:36 +02:00
694f8d784c dsp/tools: unittest sat_add 2017-06-22 11:29:56 +02:00
bd1438d28e sawg: wrap limits init values 2017-06-22 10:26:29 +02:00
cccd01e81e sawg: cleanup sat_add logic 2017-06-22 10:26:29 +02:00
5f6e665158 test/sawg: patch delay_mu 2017-06-22 10:26:29 +02:00
570f2cc1ff dsp/tools/SatAdd: fix reuse of clipped signal 2017-06-22 10:26:29 +02:00
4b3aad2563 sawg: clean up Config
* unify I and Q data limiters. there is no conceivable way why they
would be different.
* reorder clr bits to be like consistent
* move the sat add limiter to before the hbf again
2017-06-22 10:26:29 +02:00
f4c6879c76 sawg: special case Config RTIO address 2017-06-22 10:26:29 +02:00
ff0da2c9fc sawg: stage code for y-data exchange on channels 2017-06-22 10:26:29 +02:00
b6569df02f dsp/tools: clean up SatAddMixin logic 2017-06-22 10:26:29 +02:00
74cf074538 drtio: remove sawg_3g from example targets, add converter SPI bus from FMC-EBZ at all times 2017-06-21 17:01:52 +08:00
0d8067256b rtio: refactor RelaxedAsyncResetSynchronizer 2017-06-18 14:37:08 +02:00
424b2bfbd8 rtio: describe rio and rio_phy domains a bit more 2017-06-17 12:21:07 +02:00
219dfd8984 rtio: add one register level for rio and rio_phy resets
* This should give Vivado some wiggle room during PnR.
* It needs three new clock domains which is ugly. But since
AsyncResetSynchronizer can only drive clock domains resets directly
there seems to be no other way to add one register level currently.
2017-06-17 12:17:48 +02:00
e19bfd4781 test_sawg_fe: add ref_multiplier to simulated core 2017-06-16 19:45:24 +02:00
2a76034fbc cri: add note about clearing of o_data 2017-06-16 19:06:00 +02:00
3f37870e25 sawg: register pre-hbf adder 2017-06-13 18:15:44 +02:00
e229edd5d5 sawg: add register after hbf for timing 2017-06-12 23:08:27 +02:00
315338fca9 test/sawg: test HBF overshoot, fix sim patching 2017-06-12 20:35:47 +02:00
9a8a7b9102 sawg: handle clipping interpolator
* give 1 bit headroom to interpolator to handle overshoot
* fix Config limiter widths (NFC)
* move clipper to behind the HBF to correctly shield DUC

This leaves a factor of two headroom for the sum of the following
effects:

  * HBF overshoot (~15 % of the step)
  * A1/A2 DDS sum

While this is technically not sufficient and can still lead to
overflows, it is unlikely that one would trigger those. It would require
doing large amplitude A1, large amplitude A2 and additionally doing
amplitude/phase jumps that would overshoot the HBF. No sane person would
try that, right?

closes #743
2017-06-12 20:33:54 +02:00
1fb3995ffc Revert "fir/ParallelHBFUpsampler: add headroom (gain=2)"
This reverts commit 6ac9d0c41e.

Overshooting behavior must to be handled outside the FIR.
2017-06-12 20:07:25 +02:00
332bcc7f3b fir: check widths 2017-06-12 20:07:23 +02:00
39a1dcbb3d test/fir: look at overshoot behavior 2017-06-12 20:06:07 +02:00
6ac9d0c41e fir/ParallelHBFUpsampler: add headroom (gain=2)
This addresses part of #743
2017-06-12 18:59:45 +02:00
bfc224d4ba phaser: adjust to new jesd 2017-05-22 19:59:53 +02:00
679060af1d phaser: enable dma 2017-05-22 19:32:34 +02:00
4901cb9a8a sawg: fix clr width 2017-05-22 17:46:55 +02:00
253ee950f6 sawg: fix config channel addr 2017-05-22 17:45:14 +02:00
9ab63920e0 Remove Pipistrello support
Closes #658
Closes #381
2017-05-15 17:17:44 +08:00
170d2886fd Merge branch 'pdq'
* pdq:
  pdq: documentation
  pdq2 -> pdq
  pdq2: use 16 bit data, buffered read_mem()
  spi: style
  pdq2: mem_read
  pdq2: align subsequent writes to end
  sma_spi: undo cri_con
  pdq2: memory write, kernel_invariants
  sma_spi: cri/cd changes
  sma_spi: LVCMOS25
  coredevice.spi: kernel invariants and style
  sma_spi: free up user_sma pins
  sma_spi: add demo target with SPI on four SMA
  pdq2: memory write
  pdq2: crc/frame register accessors
  doc: pdq2 spi backend
  pdq2: config writes
2017-05-12 11:46:45 +02:00
Florent Kermarrec
79c339d4ac gateware/targets/phaser: jesd core now handles jsync completely 2017-04-26 22:25:08 +02:00
Florent Kermarrec
0546affd4c gateware/target/phaser: jesd start signal renamed to jsync 2017-04-26 12:27:40 +02:00
ed8edf318d sma_spi: undo cri_con 2017-04-08 17:19:35 +02:00
16b7f8f50c sma_spi: cri/cd changes 2017-04-08 17:16:19 +02:00
1e6e81a19e sma_spi: LVCMOS25 2017-04-08 17:16:19 +02:00
555b3c38c1 sma_spi: free up user_sma pins 2017-04-08 17:16:19 +02:00
2c7c6143ab sma_spi: add demo target with SPI on four SMA 2017-04-08 17:16:19 +02:00
c2667debf8 drtio: test replace in RTL simulation 2017-04-06 16:33:59 +08:00
729e7b52f0 drtio: collision/replace fixes 2017-04-06 16:33:49 +08:00
83d87b5805 drtio: remove outdated comment 2017-04-06 12:45:10 +08:00
c0100ebc56 rtio: fix indentation 2017-04-06 12:08:13 +08:00
207453efcd rtio: add a missing case for collision reporting 2017-04-06 11:28:16 +08:00
674bf82f3a gateware: add cri_con CSRs to all DMA-capable targets 2017-04-06 01:14:09 +08:00
5e3aef45dc drtio: support collision/replace + detect sequence errors at satellite 2017-04-06 01:06:56 +08:00
whitequark
17b5388259 gateware: remove one stray CRI arbiter remnant. 2017-04-05 16:38:56 +00:00
whitequark
464202d0aa gateware: connect CRI switch to kernel CPU. 2017-04-05 16:10:53 +00:00
whitequark
47632f81b1 gateware: CRIArbiter -> CRISwitch. 2017-04-05 16:10:39 +00:00
whitequark
391660e545 gateware: simplify the CRI arbiter to use a plain mux. 2017-04-05 15:09:19 +00:00
12249dac57 rtio: do not clear asynchronous error flags on RTIO reset 2017-04-03 00:20:30 +08:00
db3118b916 drtio: use BlindTransfer for error reporting 2017-04-03 00:18:07 +08:00
8c414cebc7 drtio: report busy errors 2017-04-03 00:11:08 +08:00
008678b741 drtio: add infrastructure for reporting busy/collision errors 2017-04-02 23:45:55 +08:00
0a687b7902 drtio: report satellite errors through firmware 2017-04-01 12:18:00 +08:00
28211e0b32 gateware: reset RTIO DMA core when kernel CPU is reset 2017-03-31 15:35:28 +08:00
200c499114 test: change base address in DMA simulation testbench 2017-03-31 13:17:00 +08:00
ea3af1e20e drtio: remove obsolete CSR accesses from test 2017-03-27 16:44:22 +08:00
b74d6fb9ba make collision and busy asynchronous errors, and simplify CPU/gateware handshake for output errors and reads 2017-03-27 16:32:23 +08:00
whitequark
4de336fbe9 gateware: reverse bytes of SDRAM word, not bits. 2017-03-17 11:16:46 +00:00
whitequark
6b63322106 gateware: reverse SDRAM words in RTIO DMA engine. 2017-03-17 07:29:28 +00:00
whitequark
4b14887ddb gateware: work around ISE/Vivado bugs with very wide shifts. 2017-03-17 07:29:28 +00:00
whitequark
4beda73217 firmware: don't build libdyld through misoc. 2017-03-14 08:33:31 +00:00
a7de58b604 rtio: Inout → InOut 2017-03-14 14:18:55 +08:00
13ae1d1a38 drtio: input unittest 2017-03-14 14:14:55 +08:00
56fd9b3b4b drtio: input fixes 2017-03-14 14:14:43 +08:00
95ede18809 drtio: support PHY latency compensation 2017-03-14 00:01:38 +08:00
497c795d8c drtio: input support (untested) 2017-03-13 23:54:44 +08:00
d1b9f9d737 drtio: rt_packets → rt_packet 2017-03-13 00:10:07 +08:00
6b7c781ff2 drtio: introduce 'standard request' interface in RT packet layer 2017-03-13 00:08:03 +08:00
2b8729f326 drtio: clear any read request on satellite reset 2017-03-13 00:00:38 +08:00
1e47e638bb drtio: implement inputs in RTPacketSatellite, reorganize code 2017-03-07 00:46:59 +08:00
1e6a33b586 rtio: handle input timeout in gateware
The information passed by the runtime will be used by the DRTIO core
to poll the remote side appropriately.
2017-03-03 17:37:47 +08:00
d2f2415b50 analyzer: use CRI and connect at RTIO core
This causes DMA events to be included in analyzer traces.
2017-03-02 18:47:56 +08:00
7d6ebabc1b reorganize core device communication code 2017-02-27 18:37:30 +08:00
f017d1771f gateware: remove unused configs in targets (not needed with new moninj) 2017-02-25 12:14:56 +08:00
360be0098f drtio: map local RTIO core on lower channels 2017-02-24 18:15:27 +08:00
b455ea447d gateware: add moninj to drtio targets 2017-02-21 21:54:47 +08:00
c66efc0279 moninj: do not require a rsys clock domain 2017-02-20 15:52:48 +08:00
c022b53578 kernel_cpu: enable perf counters 2017-02-18 14:09:12 +01:00
935799dfb7 drtio: fix satellite transceiver clocking 2017-02-04 19:18:35 +08:00
whitequark
b9cbedceb1 firmware: migrate last vestiges of the old runtime build system. 2017-02-03 12:59:35 +00:00
a8ecbd6041 firmware: do not attempt to build Si5324 code when gateware does not support it 2017-02-03 12:27:13 +08:00
d181989de9 drtio: reset Si5324 at each boot 2017-02-03 12:00:58 +08:00
b3697f951a drtio: forward clocks to SMA connectors for debugging 2017-02-03 12:00:36 +08:00
aafefee7f5 targets: make number of ethmac slots consistent 2017-02-02 23:02:51 +08:00
whitequark
44a9a79f96 firmware: port allocator to Rust. 2017-02-02 10:55:35 +00:00
f512ea42dc drtio: initialize si5324 in firmware 2017-02-02 18:11:24 +08:00
whitequark
b95db4fa4e Use four ethmac buffers instead of two.
This should address an issue where the host sends a packet burst,
the second packet in a burst gets dropped, the rest also gets
dropped since smoltcp doesn't do reassembly, and the entire dance
is repeated on every retransmit.
2017-01-30 07:42:27 +00:00
9800acea92 drtio: program Si5324 for 150MHz in 3G config 2017-01-30 14:50:12 +08:00
7daab07a29 drtio: fix syntax/import 2017-01-30 13:01:45 +08:00
d8e9949266 drtio: initialize AD9516 clock chip 2017-01-30 11:06:45 +08:00
f6024b6c9a drtio: fix ad9154 extension registration 2017-01-30 10:59:22 +08:00
43aad0914e python3.5 -> python3
Many things also work with Python 3.6.
2017-01-30 09:24:43 +08:00
657afd770e artiq/test/gateware -> artiq/gateware/test
This allows gateware simulations to be skipped or not considered for coverage when using test discovery.
2017-01-30 09:00:55 +08:00
94b0783897 drtio: remove support for transceiver SMAs
Passive SFP cables do not require bitstream rebuilds and do not cause weird transceiver failures.
2017-01-27 23:33:50 +08:00
whitequark
de17908b38 Revert "Globally update UART baudrate to 921600."
This reverts commit b29e2d5bfe.

This broke flterm firmware upload, which was the entire point
of the whole exercise.
2017-01-25 00:31:28 +00:00
whitequark
b29e2d5bfe Globally update UART baudrate to 921600. 2017-01-24 22:25:58 +00:00
whitequark
527b1e986c firmware: integrate smoltcp instead of lwip. 2017-01-23 13:59:34 +00:00
28a41a2f60 gateware: fix aeb1ba847 2017-01-18 17:11:02 -06:00
2a7a8f91ca gateware: fix import 2017-01-18 16:51:30 -06:00
ce31ffddb0 firmware: add satellite manager
The code duplication with the runtime should be cleaned up later.
2017-01-18 16:50:32 -06:00
b40953800a gateware: soc -> amp.soc 2017-01-18 15:28:14 -06:00
aeb1ba8471 gateware: use default MiSoC timer 2017-01-18 15:22:33 -06:00
b8d89d56b1 drtio: add GenericRXSynchronizer 2017-01-15 13:44:43 -06:00
0edffb54c2 drtio: fix packet truncation detection in RTPacketSatellite 2017-01-13 09:29:22 -06:00
6805feb494 drtio: report truncated packets 2017-01-12 23:44:45 -06:00
7c699e2f80 drtio: add FIFO space request count debug API 2017-01-11 13:48:14 -06:00
c25186fae1 drtio: print packet error descriptions in log 2017-01-10 18:03:01 -06:00
98598df78e rtio: keep retrying on get FIFO space timeout 2017-01-10 16:12:32 -06:00
e624f45369 drtio: remove FIFO empty local detection optimization
It optimizes a marginal case, it is difficult to get right
(need to know the size of the FIFO for each channel), and
it adds complexity and potential bug sources.
2017-01-10 14:31:46 -06:00
f75fffcf96 drtio: fix satellite RX data corruption 2017-01-10 14:29:30 -06:00
fe53bab953 targets: kc705 -> kc705_dds 2017-01-05 18:40:56 +01:00
082fdaf450 move i2c to libboard, do bit-banging on comms CPU 2017-01-04 21:04:38 +01:00
86f6b391b7 ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
c08fc8aae9 firmware: support moninj without DDS. Closes #650 2017-01-04 11:26:02 +01:00
455250b3f9 remove DDS_AD9914 and DDS_ONEHOT_SEL 2017-01-03 22:04:25 +01:00
fbf5a4d4a2 Merge branch 'phaser2-rust-init' 2017-01-03 21:31:21 +01:00
9a80b8d533 spi: fix xfers with full data_width (closes #615)
misoc 15000af43611bbe8be13cb2b016e408f043202cd
2017-01-03 19:51:14 +01:00
7ff77bceac move AD9616 and AD9154 initialization to firmware 2017-01-03 16:11:38 +01:00
417708af90 phaser: add note about DDS defines (#650) 2017-01-02 22:15:21 +01:00
f5f662200b fir: streamline, optimize DSP extraction, left-align inputs 2016-12-20 21:39:51 +01:00
cfb66117af fir: size hint for pre-adder 2016-12-20 17:58:06 +01:00
f310274e39 fir: cleanup halfgen4 2016-12-20 17:58:06 +01:00
6b998581cc rtio: use same reset for counter_rtio whatever the interface delay is 2016-12-15 09:28:13 +08:00
115ea67860 fir: automatically use transposed topology 2016-12-14 19:16:07 +01:00
a451b675c9 Revert "fir: different adder layout"
This reverts commit 6f50e77b409c293c1905f28e69d79403a0803866.
2016-12-14 19:16:07 +01:00
93076b8efa fir: different adder layout 2016-12-14 19:16:07 +01:00
61abd994e9 Revert "fir: force dsp48"
This reverts commit 0ad433832d1b6dcd803ffa086ae73b2ee0568326.
2016-12-14 19:16:07 +01:00
641d109786 fir: force dsp48 2016-12-14 19:16:07 +01:00
8381db279f sawg: wire up all HBF outputs, latency compensation in phys, simplify 2016-12-14 19:16:07 +01:00
6cdb96c5e0 rtio: add support for latency compensation in phy
* if multiple RTIO channels influence the same data stream and physical
output channel (see SAWG) differential latency needs to be compensated
* this is a NOP for phys with zero delay (default)
* if delay==1, it adds one timestamp-wide register
* if delay >1, it adds one adder and one register
* latency compensation using (~10-50 deep) delay lines is about as
expensive as a single adder+register but very tedious to implement
2016-12-14 19:16:07 +01:00
4c27029be0 sawg: fix limit regs 2016-12-14 19:16:07 +01:00
e9592105ce drtio: fix aux controller clock domain mistakes 2016-12-14 10:16:45 +08:00
527757b471 kc705_drtio: use ad9154_fmc_ebz 2016-12-13 14:30:26 +08:00
3b5abae935 drtio: fix clock domain conflict 2016-12-13 14:19:49 +08:00
03d13d3811 phaser: dma/drtio changes 2016-12-12 17:46:36 +01:00
c63fa46430 Merge branch 'phaser2'
* phaser2: (157 commits)
  sawg/hbf: tweak pipeline for timing
  fir: register multiplier output
  conda/phaser: build-depend on numpy
  sawg: reduce coefficient width
  sawg: fix latency
  test/fir: needs mpl. don't run by default
  test/sawg: patch spline
  sawg: use ParallelHBFCascade to AA [WIP]
  fir: add ParallelHBFCascade
  fir: add ParallelFIR and test
  gateware/dsp: add FIR and test
  README_PHASER: update
  sawg: documentation
  sawg: extract spline
  sawg: document
  sawg: demo_2tone
  sawg: round to int64
  gateware/phaser -> gateware/ad9154_fmc_ebz
  phaser: fix typo
  sawg: merge set/set64
  ...
2016-12-12 17:31:39 +01:00
4b61020b27 drtio: reset more local state 2016-12-12 18:48:10 +08:00
d99e64effd drtio: clear any stale FIFO space reply 2016-12-12 18:02:56 +08:00
4c59c0fecf Revert "drtio: order resets wrt writes"
This reverts commit 9a048c2b3a.
2016-12-12 17:49:07 +08:00
8f747fa209 drtio: clear underflow and sequence error on reset 2016-12-12 17:39:14 +08:00
7196bc21c1 rtio: simplify error reset logic
Channel is always selected when reset is issued.
2016-12-12 17:35:10 +08:00
9a048c2b3a drtio: order resets wrt writes 2016-12-12 17:18:07 +08:00
0a9f69a3ed kc705_drtio_master: add missing rtio_core CSRs 2016-12-09 19:23:36 +08:00
bc36bda94a perform RTIO init on comms CPU side 2016-12-09 14:16:55 +08:00
f6071a5812 sawg/hbf: tweak pipeline for timing 2016-12-08 17:00:53 +01:00
b7a308d33d fir: register multiplier output 2016-12-08 17:00:39 +01:00
18e3f58c22 sawg: reduce coefficient width 2016-12-08 16:14:32 +01:00
598da09a93 sawg: fix latency 2016-12-08 15:53:35 +01:00
3eef6229cc sawg: use ParallelHBFCascade to AA [WIP] 2016-12-08 15:32:57 +01:00
a629eb1665 fir: add ParallelHBFCascade 2016-12-08 15:30:26 +01:00
d303225249 fir: add ParallelFIR and test 2016-12-08 15:21:04 +01:00
7e0f3edca5 gateware/dsp: add FIR and test 2016-12-07 19:14:23 +01:00
4c3717932e drtio: link layer debugging CSRs 2016-12-07 23:03:14 +08:00
b311830fc4 kc705: fix drtio_aux address conflict 2016-12-06 18:28:48 +08:00
4669d3f02f kc705_drtio_satellite: add MiSoC system, hook up auxiliary controller 2016-12-06 14:56:42 +08:00
f4b7d39a69 kc705_drtio_master: hook up auxiliary controller 2016-12-06 14:56:15 +08:00
f3c50a37ca rtio: always read full DMA sequence 2016-12-06 01:05:47 +08:00
c413d95b49 rtio: fix DMA get_csrs 2016-12-05 18:12:09 +08:00
b677c69faf rtio: fix handling of o_status in DMA 2016-12-05 18:01:48 +08:00
75ea13748a rtio: fix DMA data MSB and stop signaling, self-checking unittest 2016-12-05 18:01:48 +08:00
a5834765d0 rtio: more DMA fixes, better stopping mechanism 2016-12-05 18:01:48 +08:00
30bce5ad35 rtio: DMA fixes 2016-12-05 18:01:48 +08:00
88ad054ab6 Merge branch 'drtio' 2016-12-03 23:25:17 +08:00
5d145ff912 drtio: add false paths between sys and transceiver clocks 2016-12-03 23:03:01 +08:00
4b97b9f8ce drtio: add clock constraints 2016-12-03 22:17:29 +08:00
e747696aaa Merge remote-tracking branch 'm-labs/phaser2' into phaser2
* m-labs/phaser2:
  phaser: fix typo
2016-12-02 14:11:56 +01:00
cbf1004df3 gateware/phaser -> gateware/ad9154_fmc_ebz 2016-12-02 14:11:41 +01:00
6353f6d590 drtio: support different configurations and speeds 2016-12-02 17:22:22 +08:00
3cee269afe phaser: fix typo 2016-12-02 11:06:45 +08:00
3931d8097b rtio: fix DMA TimeOffset stream.connect 2016-12-01 16:43:46 +08:00
d4cb1eb998 kc705: integrate DMA 2016-12-01 16:31:00 +08:00
7c59688a12 rtio: simple DMA fixes 2016-12-01 16:30:48 +08:00
46dbc44c8f rtio: export DMA and CRIInterconnectShared 2016-12-01 16:30:29 +08:00
6c97a97d8c rtio: support single-master CRI arbiter 2016-12-01 16:30:11 +08:00
a318243083 rtio: CRI arbiter (untested) 2016-12-01 15:41:43 +08:00
cd3f68ba76 rtio: DMA core (untested) 2016-11-30 18:43:19 +08:00
d8b5eac856 sawg: style 2016-11-29 20:51:40 +01:00
27160f5912 phaser: make sysref input only for timing 2016-11-29 15:28:10 +01:00
cf342eca6e kc705_drtio_master: fix number of fine RTIO timestamp bits 2016-11-29 10:44:27 +08:00
f4c6d6eb69 kc705_drtio_master: fix number of fine RTIO timestamp bits 2016-11-28 15:18:54 +08:00
85f2467e2c rtio: fix RTIO/DRTIO timestamp resolution discrepancy 2016-11-28 15:01:46 +08:00
9fdd29ddae drtio: connect KernelInitiator correctly 2016-11-28 14:36:18 +08:00
5460202220 drtio: typo 2016-11-28 14:35:21 +08:00
4e1b497742 drtio: typo 2016-11-28 14:34:58 +08:00
c419c422fa drtio: support for local RTIO core 2016-11-28 14:33:26 +08:00
046b8bfd33 drtio: fix transmit datapath with transceiver width > max packet width 2016-11-27 13:19:12 +08:00
0903964488 drtio: large data fixes 2016-11-27 02:12:50 +08:00
8090abef5d drtio: large data support 2016-11-25 17:04:09 +08:00
55e37b41ec phaser: use ttl_simple.Input for sync 2016-11-24 15:55:26 +01:00
8060652913 phaser: use Inout_8X 2016-11-24 15:21:03 +01:00
617650f3b2 phaser: extract target 2016-11-24 15:20:51 +01:00
1c84d1ee59 Merge branch 'master' into phaser2
* master:
  rtio: support differential ttl
  RELEASE_NOTES: int(a, width=b) removal, use int32/64
  pc_rpc: use ProactorEventLoop on Windows (#627)
2016-11-24 15:05:49 +01:00
95c885b580 rtio: support differential ttl 2016-11-24 15:04:12 +01:00
7cd27abaa6 drtio: do not reset remote TSC on reset command 2016-11-24 00:09:53 +08:00
2d62a89143 rtio: use large data register 2016-11-23 23:23:27 +08:00
07f2d84275 drtio: remote resets 2016-11-23 23:19:31 +08:00
9941f3557d rtio: use only CRI commands for rio/rio_phy resets 2016-11-23 23:19:14 +08:00
347609d765 rtio: auto clear output event data and address
This is to support channels where variable length
event data is well-defined through zero-padding.
E.g. in the case of `Spline` zero-padding of events naturally
corresponds to low-order knots.

Use timestamp change as trigger. This assumes that writes to the
timestamp register always precede address and data writes.
It does not break support for ganged writes of the same event
timestamp and data/address to multiple channels or
channel-addresses.
2016-11-23 15:03:36 +01:00
32fdacd95a Merge remote-tracking branch 'm-labs/master' into phaser2
* m-labs/master:
  runtime: don't attempt to perform writeback if disabled in kernel.
  runtime: print trace level log messages to UART during startup.
  runtime: support for targets without RTIO log channel
  runtime: support for targets without I2C
  kc705: remove stale DDS definition
  runtime: show a prompt to erase startup/idle kernels.
2016-11-23 14:56:29 +01:00
d400c81cb2 rtio: remove debug print 2016-11-23 13:37:14 +08:00
4e931c7dd2 rtio: fix timestamp shift 2016-11-23 13:36:30 +08:00
e532261a9b drtio: fix FullMemoryWE usage 2016-11-23 12:25:43 +08:00
0443f83d5e runtime: support for targets without RTIO log channel 2016-11-23 10:50:55 +08:00
0c49679984 runtime: support for targets without RTIO log channel 2016-11-23 10:48:26 +08:00
ffefdb9269 rtio: fix counter readback 2016-11-23 00:54:47 +08:00
aa00627c0e rtio: fix CRI CSRs 2016-11-22 22:57:04 +08:00
fbd83cf9ee kc705: remove stale DDS definition 2016-11-22 22:48:22 +08:00
9acc7d135e gateware: common RTIO interface 2016-11-22 22:46:50 +08:00
0aaf120ca7 kc705: remove stale DDS definition 2016-11-22 22:46:19 +08:00
3459793586 Merge branch 'master' into drtio 2016-11-22 15:15:22 +08:00
4160490e0a Merge branch 'phaser' into phaser2
* phaser: (23 commits)
  RELEASE_NOTES: update
  pipistrello: add some inputs
  Remove last vestiges of nist_qc1.
  Fully drop AD9858 and kc705-nist_qc1 support (closes #576).
  coredevice.dds: reimplement fully in ARTIQ Python.
  compiler: unbreak casts to int32/int64.
  analyses.constness: fix false positive on x[...].
  inferencer: significantly improve the op-assignment diagnostic.
  Fix tests.
  Move mu_to_seconds, seconds_to_mu to Core.
  artiq_devtool: don't crash on invalid utf-8.
  artiq_devtool: detect a race condition during connect.
  llvm_ir_generator: handle no-op coercions.
  conda: use development version of migen/misoc
  Revert accidentally committed code.
  Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623"
  analyses.invariant_detection: implement (#622).
  Fix whitespace.
  coredevice.dds: work around the round(numpy.float64()) snafu.
  coredevice.dds: update from obsolete int(width=) syntax (fixes #621).
  ...
2016-11-21 17:29:46 +01:00
f7e8961ab0 Merge branch 'master' into phaser
* master: (23 commits)
  RELEASE_NOTES: update
  pipistrello: add some inputs
  Remove last vestiges of nist_qc1.
  Fully drop AD9858 and kc705-nist_qc1 support (closes #576).
  coredevice.dds: reimplement fully in ARTIQ Python.
  compiler: unbreak casts to int32/int64.
  analyses.constness: fix false positive on x[...].
  inferencer: significantly improve the op-assignment diagnostic.
  Fix tests.
  Move mu_to_seconds, seconds_to_mu to Core.
  artiq_devtool: don't crash on invalid utf-8.
  artiq_devtool: detect a race condition during connect.
  llvm_ir_generator: handle no-op coercions.
  conda: use development version of migen/misoc
  Revert accidentally committed code.
  Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623"
  analyses.invariant_detection: implement (#622).
  Fix whitespace.
  coredevice.dds: work around the round(numpy.float64()) snafu.
  coredevice.dds: update from obsolete int(width=) syntax (fixes #621).
  ...
2016-11-21 17:29:39 +01:00
93c310dfa5 pipistrello: add some inputs 2016-11-21 23:43:41 +08:00
whitequark
6aa5d9f6c6 Remove last vestiges of nist_qc1. 2016-11-21 15:36:22 +00:00
whitequark
5e8888d5f3 Fully drop AD9858 and kc705-nist_qc1 support (closes #576). 2016-11-21 15:14:17 +00:00
whitequark
f4b7666768 coredevice.dds: reimplement fully in ARTIQ Python.
This commit also drops AD9858 support from software.
2016-11-21 15:13:26 +00:00
174c4be218 phaser: false paths sys<->{jesd,phy.tx} 2016-11-21 09:57:33 +01:00
74e5013fe5 sawg: fix b delay width 2016-11-20 16:39:22 +01:00
ad1049d59a Revert "gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623"
This reverts commit 4a62e09bd4.
2016-11-20 21:35:07 +08:00
whitequark
30598720f4 Fix whitespace. 2016-11-20 09:50:00 +00:00
David Leibrandt
4a62e09bd4 gateware: increase RTIO FIFO sizes for NIST_CLOCK. Closes #623 2016-11-20 15:22:32 +08:00
12e39a64cf sawg: reduce f0 oscillator width to 32 2016-11-19 17:07:07 +01:00
04813ea29b sawg: wir up limiting, saturating addition 2016-11-19 16:12:27 +01:00
e53d0bcd5b dsp: add limits support to SatAddMixin 2016-11-19 16:12:27 +01:00
97a54046e8 rtio: auto clear output event data and address
This is to support channels where variable length
event data is well-defined through zero-padding.
E.g. in the case of `Spline` zero-padding of events naturally
corresponds to low-order knots.

Use timestamp change as trigger. This assumes that writes to the
timestamp register always precede address and data writes.
It does not break support for ganged writes of the same event
timestamp and data/address to multiple channels or
channel-addresses.
2016-11-19 16:12:27 +01:00
b714137f76 phaser: 150 MHz rtio/jesd clock 2016-11-19 13:16:30 +01:00
02adae7397 drtio: fix link shutdown 2016-11-19 11:01:33 +08:00
381e58434f drtio: handle link restarts at transceiver level 2016-11-19 10:46:56 +08:00
0ee47e77ae phaser: fix widths 2016-11-18 17:24:11 +01:00
bcde26f990 Revert "phaser: cap phy data width to 64 temporarily"
This reverts commit 342b9e977e.
2016-11-18 17:08:44 +01:00
ba94ed8f4b drtio: check for absence of disparity errors before claiming RX ready 2016-11-19 00:05:59 +08:00
342b9e977e phaser: cap phy data width to 64 temporarily 2016-11-18 15:46:59 +01:00
14ddcd2e30 Revert "dsp/Delay: reset_less"
for now

This reverts commit 98193d6fa1.
2016-11-18 15:25:42 +01:00
d678bb3fb6 phaser: update sawg tests 2016-11-18 15:23:56 +01:00
4d07974a34 drtio: reset link from CPU 2016-11-18 17:45:33 +08:00
f040e27041 drtio: add timeout on FIFO get space request 2016-11-18 17:44:48 +08:00
bb047aabe9 drtio: simpler link layer 2016-11-17 22:32:39 +08:00
51f23feeac dsp: implement sawg features 2016-11-17 03:20:37 +01:00
98193d6fa1 dsp/Delay: reset_less 2016-11-17 02:36:29 +01:00
424a1f8f4e dsp: move test tools 2016-11-16 13:39:19 +01:00
140bb0ecee drtio: aux controller fixes 2016-11-16 19:44:03 +08:00
6c9965b444 drtio: aux controller fixes 2016-11-15 12:02:41 +08:00
e1394db861 drtio: aux controller minor fixes 2016-11-14 17:26:30 +08:00
84bd962ed5 drtio: integrate aux controller 2016-11-14 17:20:47 +08:00
a4d92716da drtio: fix aux receiver, add aux transmitter 2016-11-14 17:18:54 +08:00
b9ce2bb1f0 Merge branch 'phaser' into phaser2
* phaser: (127 commits)
  phaser: use misoc cordic
  phaser: fix DDS dummy cfg
  runtime: disable the Nagle algorithm entirely.
  runtime: buffer RPC send packets.
  runtime: don't print debug messages to the UART.
  runtime: print microsecond timestamps in debug messages.
  artiq_devtool: abort if build failed.
  conda: bump llvmlite-artiq dep.
  conda: bump llvmlite-artiq dep.
  llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
  artiq_devtool: more robust port forwarding.
  setup: remove paramiko dependency (optional and developer-only)
  artiq_devtool: implement.
  artiq_compile: actually disable attribute writeback.
  conda: use pythonparser 1.0.
  conda: tighten pythonparser dependency (fixes #600).
  doc: clarify kernel_invariant doc (fixes #609).
  compiler: Emit all-kernel_invariant objects as LLVM constants
  conda: update for LLVM 3.9.
  add has_dds, use config flags
  ...
2016-11-13 17:30:37 +01:00
70a70320bd phaser: use misoc cordic 2016-11-13 17:29:38 +01:00
2e482505c6 phaser: fix DDS dummy cfg 2016-11-13 17:08:59 +01:00
f2f131e0fb drtio: add aux receiver (untested) 2016-11-14 00:04:53 +08:00
aedb6747f2 Merge branch 'master' into phaser
* master: (47 commits)
  runtime: disable the Nagle algorithm entirely.
  runtime: buffer RPC send packets.
  runtime: don't print debug messages to the UART.
  runtime: print microsecond timestamps in debug messages.
  artiq_devtool: abort if build failed.
  conda: bump llvmlite-artiq dep.
  conda: bump llvmlite-artiq dep.
  llvm_ir_generator: use !{→unconditionally.}invariant.load metadata.
  artiq_devtool: more robust port forwarding.
  setup: remove paramiko dependency (optional and developer-only)
  artiq_devtool: implement.
  artiq_compile: actually disable attribute writeback.
  conda: use pythonparser 1.0.
  conda: tighten pythonparser dependency (fixes #600).
  doc: clarify kernel_invariant doc (fixes #609).
  compiler: Emit all-kernel_invariant objects as LLVM constants
  conda: update for LLVM 3.9.
  add has_dds, use config flags
  Revert "Revert "Revert "Revert "Update for LLVM 3.9.""""
  Revert "Revert "Revert "Update for LLVM 3.9."""
  ...
2016-11-13 16:54:28 +01:00
8a48d6d66e drtio: fix typo 2016-11-09 22:15:42 +08:00
863934c4fa drtio: more reliable link layer init 2016-11-09 22:03:47 +08:00
99ad9b5917 add has_dds, use config flags 2016-11-08 23:33:03 +08:00
95acc9b9d4 drtio: allow specifying 7series RXSynchronizer initial phase 2016-11-08 16:52:40 +08:00
bcb5053fb6 drtio: fix master TSC KCSR readout 2016-11-08 16:40:50 +08:00
c4cd269afc Merge branch 'master' into drtio 2016-11-06 00:13:32 +08:00
d158c69be0 phaser: fix frequency comment 2016-11-05 16:54:23 +01:00
47b9868c68 kc705_drtio_master: pretend drtio is rtio 2016-11-05 23:48:29 +08:00
de065b7578 kc705_drtio_satellite: set output dir 2016-11-05 23:48:15 +08:00
de47123737 drtio: connect RST and LOCKED on 7series RXSynchronizer MMCM 2016-11-05 00:24:49 +08:00
df7294792c drtio: break some RT features into manager, add echo request CSR 2016-11-04 19:38:24 +08:00
1145a193dd drtio: fix ack of echo and set_time requests 2016-11-04 18:36:43 +08:00
3da1cce783 drtio: add packet counters 2016-11-04 17:53:42 +08:00
747da3da15 drtio: differentiate local and remote unknown packet type errors 2016-11-04 15:17:19 +08:00
f76aa249ce drtio: squelch 7series RXSynchronizer outputs when MMCM is unlocked 2016-11-04 15:16:48 +08:00
6a75837261 drtio: fix link_layer remote RX ready detection 2016-11-03 20:15:04 +08:00
1d027ffa95 drtio: fix gtx_7series comma alignment 2016-11-03 20:14:11 +08:00
ba58a8affd drtio/gtx_7series: paranoid reset deglitching 2016-11-02 18:30:22 +08:00
whitequark
00100148f1 Si5324: actually write value of N32 into registers. 2016-11-02 07:09:04 +00:00
bee9774bd5 drtio: add link layer status CSR 2016-11-02 13:09:13 +08:00
1ed3278783 remove stale TODO 2016-11-02 10:53:54 +08:00
whitequark
a6ae254796 Si5324: update to free run from XA/XB, with CKIN1 having priority. 2016-11-01 16:01:24 +00:00
whitequark
636d4efe81 gateware: rewrite mailbox to use bits_for. 2016-11-01 06:28:43 +00:00
whitequark
18ae8d54a3 gateware: fix mailbox. 2016-11-01 02:33:00 +00:00
whitequark
898a716b91 runtime: work around mor1kx ignoring low bits of reset address.
Fixes #599.
2016-10-31 18:13:15 +00:00
0c1a76d668 unify rtio/drtio kernel interface 2016-11-01 00:30:16 +08:00
whitequark
617e345d16 gateware: fix kernel CPU exec address. 2016-10-31 15:16:35 +00:00
07ad00c1ca drtio: split kernel/system CSRs 2016-10-31 18:09:36 +08:00
9aa94e1a2d adapt to migen/misoc changes 2016-10-31 00:53:01 +08:00
2392113bb6 kc705: use misoc clock for false path 2016-10-30 11:16:04 +08:00
whitequark
2ac85cd40f runtime: implement prototype background RPCs. 2016-10-29 21:34:25 +00:00
c656a53532 kc705: clean up clock constraints 2016-10-29 21:28:01 +08:00
ed4d57c638 use new Migen signal attribute API 2016-10-29 21:19:58 +08:00
da5208e160 drtio: add master gateware target 2016-10-29 17:31:15 +08:00
7c05dccf65 drtio: add support for 125MHz clock on GTX_1000BASE_BX10 2016-10-29 17:30:29 +08:00
95def81c03 drtio: squelch frame signals until link layer ready 2016-10-29 17:05:30 +08:00
4f6241283c drtio: always use NoRetiming on MultiReg inputs 2016-10-29 16:37:53 +08:00
2a1e529dcf phaser: DDS config dummies 2016-10-28 01:58:08 +02:00
6d07a16c62 Merge branch 'master' into phaser
* master: (72 commits)
  gateware: extend mailbox to 3 entries.
  master/worker_db: set default value for archive
  master: keep dataset manager consistent when set_dataset is called with contradictory attributes
  master: archive input datasets. Closes #587
  master: ensure same dataset is in broadcast and local when mutating
  scheduler: default submission arguments, closes #577
  pdq2: sync with pdq2
  doc: clarify usage of pause/check_pause, closes #571
  dashboard/datasets: use scientific spinbox and increase number of decimals, closes #572
  gateware/spi: fix import
  runtime: fix use of $(realpath) in Makefile.
  test: fix printf specifier.
  llvm_ir_generator: make sure RPC allocations are not underaligned.
  runtime: use i64 for watchdog timeout, not i32.
  runtime: port ksupport to Rust.
  runtime: remove some redundant libm functions copied inline.
  language: Add "A" (ampere) as well-known unit for arguments
  conda: misoc 0.4 (csr)
  runtime: cap log level at debug.
  runtime: discard unnecessary sections.
  ...
2016-10-28 01:40:11 +02:00
c428800caf phaser: spi, sma_gpio: 2.5 V 2016-10-27 15:53:49 +02:00
65b2e4464c phaser: sysref/sync diff term 2016-10-27 14:14:56 +02:00
ea0c304a0c phaser2: wip 2016-10-27 01:00:42 +02:00
929a7650a8 drtio: fixes 2016-10-26 22:03:44 +08:00
45621934fd drtio: forward errors to CSR 2016-10-26 22:03:05 +08:00
7f8e53aa5c drtio: more fixes and tests 2016-10-26 11:48:47 +08:00
f763b519f4 drtio: fix channel selection 2016-10-26 00:33:21 +08:00
ad042de954 drtio: fixes, basic TTL working in simulation 2016-10-25 12:41:16 +08:00
e981b23548 phaser: use misoc cordic 2016-10-24 19:33:23 +02:00
d2f776b0d0 phaser: add more tools 2016-10-24 17:39:14 +02:00
a4e85081aa drtio: more simple fixes 2016-10-24 23:32:49 +08:00
029e0d95b7 drtio: simple fixes 2016-10-24 23:10:15 +08:00
c39987b617 drtio: handle underflow/sequence error CSRs 2016-10-24 20:46:55 +08:00
7dd6eb2f5e drtio: add RT write controller 2016-10-24 19:50:13 +08:00
83bec06226 drtio: fifo level -> fifo space 2016-10-24 15:59:12 +08:00
aa8e211735 drtio/rt_packets: fix 2016-10-22 13:03:35 +08:00
449d1c4dc6 rtio: export CDC modules 2016-10-22 13:03:10 +08:00
67c19ab178 drtio: RTPacketMaster RX, untested 2016-10-22 01:04:14 +08:00
3b4a40401a drtio: RTPacketMaster TX (WIP) 2016-10-21 22:46:14 +08:00
1e313afe64 drtio: CrossDomainNotification 2016-10-21 22:45:45 +08:00
c71c4c89e0 drtio: change data direction in _CrossDomainRequest 2016-10-21 22:44:47 +08:00
whitequark
6872017449 gateware: extend mailbox to 3 entries. 2016-10-21 12:09:14 +00:00
6a88229e6a drtio: CrossDomainRequest 2016-10-20 23:37:59 +08:00
9790c5d9ed drtio/iot: FIFO level 2016-10-19 18:04:03 +08:00
71480c4d15 drtio: fix mmcm_mult 2016-10-18 17:28:03 +08:00
e7dbed3b02 gateware: KC705 satellite target 2016-10-17 19:23:45 +08:00
9752ffe3d1 drtio: various fixes 2016-10-17 19:23:08 +08:00
cce29e8b83 gateware/spi: fix import 2016-10-17 14:47:19 +08:00
b6002529cf gateware/spi: fix import 2016-10-17 14:07:11 +08:00
85834976d9 gateware/spi: fix import 2016-10-17 14:06:35 +08:00
d3b274fc4d drtio: synchronizer MMCM 2016-10-16 17:40:58 +08:00
03d3a85e75 drtio: RX clock alignment and ready 2016-10-15 18:36:27 +08:00
Florent Kermarrec
0259c80015 phaser/kc705: remove transceiver initialization workaround 2016-10-14 19:06:43 +02:00
d16068dd9b sawg: absolute phase updates 2016-10-14 12:42:08 +02:00
b41b9de905 phaser: tag jesd as clock net 2016-10-14 10:46:33 +02:00
4ea3dea217 phaser: broad spectrum antibiotics with xilinx false paths 2016-10-14 10:22:03 +02:00
e400f8d672 phaser: add two more registers before jesd 2016-10-14 09:54:56 +02:00
3c9c42c779 phaser: drive rtio from jesd-bufg 2016-10-14 02:26:19 +02:00
808874a523 phaser: drive cd_jesd with BUFG 2016-10-14 01:57:48 +02:00
342d6d756e phaser: bypass gtx phalign 2016-10-14 00:59:53 +02:00
89150c9817 phaser: 10G line rate 2016-10-14 00:53:38 +02:00
08e4aa3e3f drtio: GTX WIP 2016-10-14 00:36:13 +08:00
c548a65ec3 drtio: clock domains 2016-10-14 00:34:59 +08:00
42c6658ffe phaser: add some more blinking leds 2016-10-13 15:21:27 +02:00
6a456bd7d4 phaser: feed correct sink (crucial) 2016-10-13 15:17:38 +02:00
c8e45ae3f6 phaser: cleanup jesd phy instantiation a bit 2016-10-13 14:43:24 +02:00
78a41eec8f phaser: kc705: syntax 2016-10-13 12:38:32 +02:00
Florent Kermarrec
af0e8582a2 phaser: use new jesd clocking 2016-10-13 11:51:06 +02:00
1117fe191b phaser: support core stpl 2016-10-12 12:03:29 +02:00
f515c11f26 phaser: fix refclk period spec 2016-10-11 20:13:34 +02:00
bae5b73155 phaser: comment out stpl test 2016-10-11 19:50:19 +02:00
2b1cca2e7e phaser: stpl 2016-10-11 19:29:27 +02:00
018f6d1b52 drtio: implement basic IOT 2016-10-11 17:59:22 +08:00
18d18b6685 phaser: add sync ttl input for monitoring 2016-10-10 17:13:23 +02:00
f5f7acc1f8 ttl_simple: add pure Input
(no Tristate for internal signals)
2016-10-10 17:13:23 +02:00
a40b39e9a2 drtio: structure 2016-10-10 23:12:12 +08:00
Florent Kermarrec
c08caae171 phaser: use qpll 2016-10-10 17:05:42 +02:00
87ec333f55 drtio: implement basic writes, errors, fifo levels on satellite 2016-10-10 00:13:41 +08:00
23b3302200 drtio: implement TSC load in satellite 2016-10-07 19:30:53 +08:00
9b860b26e8 phaser: fix rtio pll inputs 2016-10-07 13:00:42 +02:00
09434ec054 phaser: also adapt rtio_crg 2016-10-07 12:44:22 +02:00
cb0d1549c6 drtio: add rt_packets TX datapath, fixes 2016-10-07 15:35:29 +08:00
Florent Kermarrec
b02a7234f6 phaser: use 125MHz refclk for jesd 2016-10-07 08:59:34 +02:00
whitequark
b52ecda1d5 runtime: make memory map saner. 2016-10-06 18:05:38 +00:00
1193ba4bf4 ad9154: merge csr spaces 2016-10-06 16:21:15 +02:00
4d87f0e9e0 phaser: instantiate jesd204b core, wire up 2016-10-06 14:44:22 +02:00
76bac21d14 drtio: RT RX datapath, untested 2016-10-06 18:51:20 +08:00
4a0eaf0f95 phaser: add jesd204b rtio dds
gateware: add jesd204b awg

gateware: copy phaser (df3825a)
dsp/tools: update satadd mixin
phaser: no DDS stubs
dsp: accu fix
phaser: cleanup/reduce

sawg: kernel support and docs

sawg: coredevice api fixes

sawg: example ddb/experiment

phaser: add conda package

examples/phaser: typo

sawg: adapt tests, fix accu stb

sawg: tweak dds parameters

sawg: move/adapt/extend tests

sawg: test phy, refactor

phaser: non-rtio spi

phaser: target cli update

phaser: ad9154-fmc-ebz pins

phaser: reorganize fmc signal naming

phaser: add test mode stubs

phaser: txen is LVTTL

phaser: clk spi xfer test

phaser: spi for ad9154 and ad9516

phaser: spi tweaks

ad9154: add register map from ad9144.xml

ad9516: add register map from ad9517.xml and manual adaptation

ad9154_reg: just generate getter/setter macros as well

ad9154: reg WIP

ad9154: check and fix registers

kc705: single ended rtio_external_clk

use single ended user_sma_clk_n instead of p/n to free up one clock sma

kc705: mirror clk200 at user_sma_clock_p

ad9516_regs.h: fix B_COUNTER_MSB

phase: wire up clocking differently

needs patched misoc

kc705: feed rtio_external_clock directly

kc705: remove rtio_external_clk for phaser

phaser: spi tweaks

ad9516: some startup

ad9516_reg fixes

phaser: setup ad9516 for supposed 500 MHz operation

ad9516: use full duplex spi

ad9154_reg: add CONFIG_REG_2

ad9154_reg: fixes

phaser: write some ad9154 config

ad9154_reg: fixes

ad9154: more init, and human readable setup

ad9154/ad9516: merge spi support

ad9154: status readout

Revert "kc705: remove rtio_external_clk for phaser"

This reverts commit d500288bb44f2bf2eeb0c2f237aa207b0a8b1366.

Revert "kc705: feed rtio_external_clock directly"

This reverts commit 8dc7825519e3e75b7d3d29c9abf10fc6e3a8b4c5.

Revert "phase: wire up clocking differently"

This reverts commit ad9cc450ffa35abb54b0842d56f6cf6c53c6fbcc.

Revert "kc705: mirror clk200 at user_sma_clock_p"

This reverts commit 7f0dffdcdd28e648af84725682f82ec6e5642eba.

Revert "kc705: single ended rtio_external_clk"

This reverts commit a9426d983fbf5c1cb768da8f1da26d9b7335e9cf.

ad9516: 2000 MHz clock

phaser: test clock dist

phaser: test freqs

ad9154: iostandards

phaser: drop clock monitor

phaser: no separate i2c

phaser: drive rtio from refclk, wire up sysref

phaser: ttl channel for sync

ad9154: 4x interp, status, tweaks

phaser: sync/sysref 33V banks

phaser: sync/sysref LVDS_25 inputs are VCCO tolerant

phaser: user input-only ttls

phaser: rtio fully from refclk

ad9154: reg name usage fix

ad9154: check register modifications

Revert "ad9154: check register modifications"

This reverts commit 45121d90edf89f7bd8703503f9f317ad050f9564.

ad9154: fix status code

ad9154: addrinc, recal serdes pll

phaser: coredevice, example tweaks

sawg: missing import

sawg: type fixes

ad9514: move setup functions

ad9154: msb first also decreasing addr

phaser: use sys4x for rtio internal ref

phaser: move init code to main

phaser: naming cleanup

phaser: cleanup pins

phaser: move spi to kernel cpu

phaser: kernel support for ad9154 spi

ad9154: add r/w methods

ad9154: need return annotations

ad9154: r/w methods are kernels

ad9154_reg: portable helpers

phaser: cleanup startup kernel

ad9154: status test

ad9154: prbs test

ad9154: move setup, document

phaser: more documentation
2016-10-05 16:17:50 +02:00
a91ed8394c rtio: add input-only channel 2016-10-05 16:17:50 +02:00
279f0d568d rtio: support differential ttl 2016-10-05 16:17:50 +02:00
1e0c6d6d5d drtio: monitor received link_init 2016-09-30 11:25:06 +08:00
cefb9e1405 drtio: add full link layer 2016-09-27 21:41:57 +08:00
08772f7a71 drtio: add RX ready signaling 2016-09-27 19:02:54 +08:00
95d7cba34a drtio: fixes, add aux packet test 2016-09-27 12:46:01 +08:00
e59142e344 drtio: use additive scrambler reset by link init 2016-09-27 11:38:05 +08:00
8a92c2c7e5 drtio: add RX link layer, fixes, simple loopback demo 2016-09-27 11:23:29 +08:00
4e47decdbc drtio: add scrambler/descrambler and test 2016-09-26 14:14:14 +08:00
fa83ad0d9c drtio: add TX link layer 2016-09-26 12:53:10 +08:00
8280e72e90 gateware: use new misoc CSR mapping API 2016-09-24 20:48:37 +08:00
2bb90a4449 pipistrello: shrink a few more fifos 2016-09-21 02:29:05 +02:00
a7dd356d30 rtio/phy/ttl: support 'set sensitivity and sample' command (#218) 2016-09-07 15:42:09 +08:00
051e6e0447 spi: use misoc SPIMachine, closes #314 2016-08-26 14:08:12 +02:00
92f3757c74 spi: give wb-reads a register level 2016-07-31 14:53:19 +02:00
454b48df97 pipistrello: shrink fifos a bit more to relax pnr 2016-07-23 12:55:49 +02:00
7a2405146a rtio: do not reset DDS and SPI PHYs on RTIO reset (#503) 2016-07-09 10:07:19 +08:00
8cb29fcb3b targets/kc705: redefine user SMAs as 3.3V IO. Closes #502 2016-07-07 14:53:01 +08:00
71921de5bd spi: do not shift when starting a xfer, closes #495 2016-07-04 12:22:47 +02:00
3bd190e624 gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
dhslichter
141edb521a qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00
90e678a442 gateware/nist_qc2: increase DDS bus drive strength. Closes #421 2016-05-03 16:29:38 +08:00
9707981c07 targets/kc705: fix default -H option 2016-04-30 00:30:24 +08:00
212ee8ca35 gateware/nist_qc2: substitute FMC 2016-04-14 01:02:34 +08:00
dhslichter
f395a630e0 Updated qc2 pinouts for SPI and 2x DDS bus, update docs 2016-04-13 18:38:34 +08:00
ed1c368e73 gateware: name targets consistently. Closes #290 2016-04-05 16:07:29 +08:00
8f54a1e619 pipistrello: sys_clk 83 -> 75 MHz
This should close #341 once migen generates stable output.
2016-03-21 13:47:32 +01:00
900b0cc629 analyzer: make byte_count 64-bit 2016-03-19 19:40:23 +08:00
0e1f75ec49 targets/kc705/qc2: hook up HPC backplane 2016-03-16 16:19:56 +08:00
1bbef94061 analyzer: fix byte_count (again) 2016-03-15 20:49:07 +08:00
85ea70a664 analyzer: fix byte_count 2016-03-15 20:33:08 +08:00
62ac4e3c2e analyzer: fix EOP generation 2016-03-15 20:25:02 +08:00
b5ec979db3 analyzer: drive wishbone cyc signal 2016-03-15 19:46:12 +08:00
8a6873cab2 analyzer: use EOP, flush pipeline on stop 2016-03-15 17:49:59 +08:00
Florent Kermarrec
8ad799a850 gateware/rtio/analyzer: use new Converter 2016-03-14 15:15:07 +01:00
de718fc819 rtio: fix different address collision detection 2016-03-10 12:15:36 +08:00
f4f95d330b Merge branch 'master' of github.com:m-labs/artiq 2016-03-10 11:15:30 +08:00
542a375305 rtio: remove NOP suppression capability
Back when RTIO was driving TTLs, this functionality made it simpler to use by removing some irrelevant underflows.

The same technique is not applicable to DDS and SPI, so the user will have to deal with such underflows.

This patch makes the behavior of RTIO more consistent and the code simpler.
2016-03-10 09:47:29 +08:00
2e39802a61 rtio/wishbone: make replace configurable 2016-03-10 09:44:05 +08:00
107e5cfbd4 gateware/rtio: factor _BlindTransfer 2016-03-09 19:07:46 +01:00
349a66124b Merge branch 'master' into rtiobusy
* master:
  coredevice: fix _DDSGeneric __init__ args
  rtio/core: fix syntax
  rtio: disable replace on rt2wb channels
  examples: dds_bus -> core_dds
  fix more multi-DDS-bus problems
  runtime: fix dds declarations
  support for multiple DDS buses (untested)
2016-03-09 17:58:58 +01:00
3f8e431de6 rtio/core: fix syntax 2016-03-09 17:10:21 +01:00
03b53c3af9 rtio: disable replace on rt2wb channels 2016-03-09 23:37:04 +08:00
446dcfbfbc Merge commit '9d1903a' into rtiobusy
* commit '9d1903a':
  coredevice/i2c,ttl,spi: consistent device get
  examples/device_db: remove --no-localhost-bind
  Monkey-patch asyncio create_server (fixes #253).
  pipistrello: drop ttls on pmod, add leds back in
  pipistrello: try with fewer leds/pmod ttl
2016-03-09 11:55:08 +01:00
f0b0b1bac7 support for multiple DDS buses (untested) 2016-03-09 17:12:50 +08:00
f33baf339f pipistrello: drop ttls on pmod, add leds back in 2016-03-08 23:34:51 +01:00
f39208c95a pipistrello: try with fewer leds/pmod ttl 2016-03-08 22:10:47 +01:00
2cb58592ff rtio: add RTIOBusy 2016-03-08 18:04:34 +01:00
0d431cb019 pipistrello: make pmod extension header, cleanup 2016-03-08 17:07:44 +01:00
a8fe3f50c3 pipistrello: grow fifos a bit (may make ise happier) 2016-03-08 16:17:37 +01:00
00d4775da5 pipistrello: shrink fifos a bit (may make ise happier) 2016-03-08 15:40:12 +01:00
9c11cda7dc pipistrello: use ttl_simple for pmod[4:8] 2016-03-08 13:52:52 +01:00
104d641c59 pipistrello: move the spi channel like kc705 2016-03-08 13:30:05 +01:00
2180c5af7c pipistrello: make pmod[4:8] available as ttls 2016-03-08 13:07:58 +01:00
e809e89571 pipistrello: adhere to pmod interface type 2 layout 2016-03-08 13:01:52 +01:00
2953b069dc rtio: when rtlink addresses are different, issue collision not replace (fixes #320) 2016-03-08 15:58:25 +08:00
71105fd0d7 rtio: collision_error -> collision 2016-03-08 15:38:35 +08:00
e8b59b00f6 soc: use add_extra_software_packages, factor builder code 2016-03-07 00:18:47 +08:00
a8a74d7840 targets/kc705: enable I2C for all hardware adapters 2016-03-05 00:19:59 +08:00
7ff0c89d51 kc705.clock: add all spi buses 2016-03-04 00:03:48 +01:00
423ca03f3b runtime: bit-banged i2c support (untested) 2016-03-03 17:46:42 +08:00
cfe72c72a2 gateware/kc705: add I2C GPIO core for QC2 2016-03-03 15:32:10 +08:00
a901971e58 gateware/soc: factor code to connect CSR device to kernel CPU 2016-03-03 15:12:15 +08:00
b662a6fcbd gateware/nist_{clock,qc2}: do not conflict with KC705 I2C 2016-03-03 15:10:50 +08:00
9af12230c8 soc: add timer to kernel CPU system 2016-03-03 13:19:17 +08:00
0c97043a20 gateware/nist_clock: pin assignment corrections from David Leibrandt 2016-03-03 10:03:49 +08:00
d3f36ce784 kc705: add false paths for ethernet phy
* vivado prefers rsys_clk over sys_clk (despite the assignment hierarchy)
  (We need DONT_TOUCH and/or KEEP verilog annotations to fix this)
2016-03-02 19:56:24 +01:00
2cc1dfaee3 kc705: move ttl channels together again, update doc 2016-03-01 19:40:32 +01:00
c2fe9a08ae gateware.spi: delay only writes to data register, update doc 2016-03-01 14:14:38 +01:00
f2ec8692c0 nist_clock: disable spi1/2 2016-03-01 01:52:46 +01:00
da22ec73df gateware.spi: rework wb bus sequence 2016-02-29 22:22:08 +01:00
12252abc8f nist_clock: rename spi*.ce to spi*.cs_n 2016-02-29 22:21:18 +01:00
7ef21f03b9 nist_clock: add SPIMasters to spi buses 2016-02-29 22:19:39 +01:00
7ab7f7d75d Merge branch 'master' into spimaster
* master:
  artiq_flash: use term 'gateware'
  targets/kc705-nist_clock: add clock generator on LA32 for testing purposes
  doc: insist that output() must be called on TTLInOut. Closes #297
  doc: update install instructions
  coredevice: do not give up on UTF-8 errors in log. Closes #300
  use m-labs setup for defaults
  fix indentation
2016-02-29 20:47:52 +01:00
5fad570f5e targets/kc705-nist_clock: add clock generator on LA32 for testing purposes 2016-03-01 00:35:26 +08:00
dd570720ac gateware.spi: ack only in cycles 2016-02-29 17:29:37 +01:00
a0083f4501 Revert "gateware/rt2wb: only input when active"
This reverts commit 1b08e65fa1.
2016-02-29 16:44:11 +01:00
cb8815cc65 Revert "gateware/rt2wb: support combinatorial ack"
This reverts commit f73228f248.
2016-02-29 16:44:04 +01:00
f73228f248 gateware/rt2wb: support combinatorial ack 2016-02-29 15:40:55 +01:00
1b08e65fa1 gateware/rt2wb: only input when active 2016-02-29 14:56:29 +01:00
572c49f475 use m-labs setup for defaults 2016-02-29 21:35:23 +08:00
eb01b0bfee gateware.spi: cleanup doc 2016-02-29 12:41:30 +01:00
948fefa69a gateware.spi: style 2016-02-29 11:48:29 +01:00
ad34927b0a spi: RTIO_SPI_CHANNEL -> RTIO_FIRST_SPI_CHANNEL 2016-02-29 11:35:49 +01:00
5480099f1b gateware.spi: rewrite counter bias for timing 2016-02-29 02:28:19 +01:00
9a1d6a51a4 gateware.spi: shorten counters 2016-02-29 01:51:33 +01:00
8d7e92ebae pipistrello: set RTIO_SPI_CHANNEL 2016-02-29 00:37:00 +01:00
9a881aa430 gateware.spi: simpler clk bias 2016-02-29 00:36:18 +01:00
d5893d15fb gateware.kc705: make xadc/ams an extension header 2016-02-28 22:41:17 +01:00
312e09150e kc705/clock: add spi bus for dac on ams101 2016-02-28 21:17:53 +01:00
f8732acece rtio.spi: drop unused argument 2016-02-28 21:06:20 +01:00
3b6999ac06 gateware.spi: refactor, sim verified 2016-02-28 20:40:06 +01:00
bd9ceb4e12 gateware.spi: add complete spi master logic 2016-02-27 22:47:16 +01:00
ade3eda19a gateware.pipistrello: use pmod for spi 2016-02-27 11:29:40 +01:00
e7146cc999 gateware.spi: design sketch 2016-02-26 17:03:08 +01:00
fb929c8599 gateware/spi: stubs 2016-02-26 13:11:10 +01:00
a8545fc1f7 targets/kc705: set up user_sma_gpio_n like other TTLs 2016-02-22 22:35:15 +08:00
4946a53456 Revert "targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance"
This reverts commit 04b0db1a91.
2016-02-22 17:52:40 +08:00
68891493a3 analyzer: move common to artiq.protocols
migen was still pulled in through rtio.__init__.py
2016-01-29 20:26:48 -07:00
d1119d7747 artiq_dir: move out of tools to unlink dependencies 2016-01-25 18:15:50 -07:00
cbb60337ae refactor Analyzer constants to unlink dependencies 2016-01-25 18:03:48 -07:00
2832d200f2 Merge remote-tracking branch 'm-labs/master' into ppp2
* m-labs/master:
  test/worker: update
  gui/log: display level and date information in tooltips
  master: add filename in worker log entries. Closes #226
  master: finer control of worker exception reporting. Closes #233
  conda: add artiq-kc705-nist_clock
  gateware: add QC1 docstring
  gateware: add clock target from David
  gateware: clean up and integrate QC2 modifications from Daniel
  add information about CLOCK hardware
2016-01-25 12:17:04 -07:00
8cbb60b370 Merge branch 'master' into ppp2
* master:
  add release notes/process
  targets/kc705: fix e664fe3
  targets/kc705: fix DDS_RTIO_CLK_RATIO for AD9914. Closes #238
  transforms.inferencer: give a suggestion on "raise Exception".
  pdq2/mediator: raise instances, not classes
  pdq2: wire up more of the pipeline
  doc: use actual version
  Fix formatting.
  doc: add artiq_flash
  versioneer: remote tag_prefix = v
2016-01-20 19:29:00 -07:00
18f0ee814d gateware: add QC1 docstring 2016-01-20 21:27:22 -05:00
db8ba8d6c1 gateware: add clock target from David 2016-01-20 21:23:49 -05:00
b3ba97e431 gateware: clean up and integrate QC2 modifications from Daniel 2016-01-20 21:17:19 -05:00
fa1afb7dd8 add information about CLOCK hardware 2016-01-20 21:06:02 -05:00
cb5fd08713 targets/kc705: fix e664fe3 2016-01-20 09:38:44 -05:00
e664fe38b0 targets/kc705: fix DDS_RTIO_CLK_RATIO for AD9914. Closes #238 2016-01-20 09:18:50 -05:00
57ce78c54d pipistrello: add rtio.Analyzer() 2016-01-18 19:17:44 -07:00
whitequark
9366a29483 Implement core device storage (fixes #219). 2016-01-10 13:04:55 +00:00
whitequark
577108554f Move kernel CPU address space up to 0x40800000. 2016-01-07 18:26:11 +00:00
87dd09a71c gateware: compress bitstreams 2016-01-06 15:40:28 -07:00
04b0db1a91 targets/kc705: pre-divide input RTIO clock to improve non-50% duty cycle tolerance 2015-12-29 17:00:57 +08:00
ba6c527819 gateware/targets: add RTIO log channels 2015-12-26 22:44:01 +08:00
080752092c gateware/rtio: add LogChannel 2015-12-26 22:43:28 +08:00
9ba8dfbf23 gateware/rtio/core: avoid potential python bug 2015-12-26 22:11:57 +08:00
8691f69a3c gateware/rtio/analyzer: suppress spurious initial reset messages 2015-12-21 18:32:08 +08:00
5769107936 gateware/rtio: keep counter clock domain transfer active during CSR reset 2015-12-20 22:12:34 +08:00
46f59b673f coredevice: analyzer message decoding 2015-12-20 14:34:16 +08:00
1638f0fa9b gateware/rtio/analyzer: fix event ordering 2015-12-19 17:04:30 +08:00
64ad38854b gateware/rtio/analyzer: fix exception message layout 2015-12-18 18:27:06 +08:00
59a3ea4f15 gateware/rtio/analyzer: fix bus write 2015-12-18 15:44:20 +08:00
4def561710 targets: integrate RTIO analyzer 2015-12-16 17:36:52 +08:00
afaad270cc rtio/analyzer: fix superficial mistakes 2015-12-16 17:36:36 +08:00
33860820b9 gateware/soc: use new SDRAM API call 2015-12-16 14:59:35 +08:00
bf29e8ddc6 kc705: make config[] usage consistent 2015-12-15 12:14:30 -07:00
4362f97d67 gateware/rtio/analyzer: complete, untested 2015-12-14 23:53:14 +08:00
b5f2e178f6 rtio/analyzer: message encoder 2015-12-14 00:37:08 +08:00
7886827b80 CSRConstant: also port DDS constants 2015-12-04 18:27:59 +08:00
5db1f9794e top.add_constant() -> top.config[] (CSRConstant)
This is to be synchronized with the corresponding change in misoc.
2015-12-04 18:27:54 +08:00
whitequark
c14299dca8 Merge branch 'new-py2llvm' 2015-11-24 03:01:54 +08:00
whitequark
9fc7a42036 pipistrello: expose LED{1..4} as RTIO channels. 2015-11-23 18:26:45 +08:00
ae99af27ee runtime,gateware: use new misoc identifier 2015-11-10 22:44:38 +08:00
e749bae302 package everything to rebuild core device binaries 2015-11-09 10:47:14 +08:00
whitequark
51f04f6311 Explicitly use the python3.5 binary everywhere. 2015-11-07 13:39:39 +03:00
ad5a32fb6e targets/kc705: remove unneeded argument on qc2 2015-11-04 20:09:37 +08:00
e26147b2ac gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
e46ba83513 rtio/dds: use rio_phy domain to reset FTW tracker. Closes #120 2015-10-04 22:53:51 +08:00
01416bb0be copyright: claim contributions
These are contributions of >= 30% or >= 20 lines (half-automated).

I hereby resubmit all my previous contributions to the ARTIQ project
under the following terms:

    This program is free software: you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation, either version 3 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.

Closes #130

Signed-off-by: Robert Jordens <jordens@gmail.com>
2015-09-06 16:08:57 -06:00
90ce54d8d5 gateware/dds/monitor: support onehot selection, strip reset 2015-08-27 15:54:01 +08:00
d38f1e6796 ad9xxx: fix gpio signal length 2015-08-22 13:12:30 +08:00
094fc1cfd1 qc2: DDS selection is active low 2015-08-22 11:49:38 +08:00
1d34c06d79 rtio: detect collision errors 2015-07-29 19:43:35 +08:00
fb339d294e serdes_s6: no need to reset 2015-07-28 12:54:31 -06:00
9ac5bc52d4 rtio: add spartan6 serdes, 4x and 8x 2015-07-27 21:01:15 -06:00
b1d58bd4c8 rtio: fix replace/sequence_error when fine_ts_width > 0 2015-07-27 12:22:35 +08:00
959b7a7b46 rtio: resetless -> reset_less 2015-07-27 11:46:56 +08:00
fe6a5c42df rtio: remove unused clk_freq argument 2015-07-27 10:57:15 +08:00
5b50f5fe05 rtio/ttl_serdes_7series: use recommended OSERDES T configuration 2015-07-27 10:50:50 +08:00
f68d5cbd73 rtio: forward rtio domain reset to rio and rio_phy domains 2015-07-27 01:52:47 +08:00
940aa815dd rtio/ttl_serdes: cleanup/rewrite 2015-07-27 01:44:52 +08:00
Yann Sionneau
d90dff4ef1 rtio: add SERDES TTL (WIP) 2015-07-26 17:40:34 +08:00
47191eda91 dds monitor: relax timing (for pipistrello) 2015-07-19 21:36:51 -06:00
66940ea815 rtio: disable NOP suppression after reset and underflow 2015-07-15 20:54:55 +02:00
34aacd3c5f complete AD9914 support (no programmable modulus, untested) 2015-07-08 17:22:43 +02:00
8a33d8c868 never stop RTIO counter 2015-07-07 15:29:38 +02:00
58c0150822 ttl: improve clockgen doc 2015-07-05 19:07:13 +02:00
753d61b38f complete support for TTL clock generator 2015-07-04 18:36:01 +02:00
2881d5f00a gateware: add RTIO clock generator 2015-07-02 18:20:26 +02:00
23eee94458 pipistrello: add notes to nist_qc1 about dds_clock
* remove xtrig from the target as it is not usually connected (used for
  dds_clock) and ignore PMT2/BTN2 as C:15 is used for dds_clock.
* this also aligns the ttl channel numbers with kc705/nist_qc1 (two pmt
  inputs followed by 16 ttl outputs followed by leds)
2015-06-28 20:56:12 -06:00
944bfafefa soc: support QC2 and AD9914 (untested) 2015-06-28 21:37:27 +02:00
Yann Sionneau
9c96ebf7d4 nist_qc2: add fmc adapter io file 2015-06-25 03:06:15 +02:00
45ec5dbe84 ad9858: make wb data 8 bit wide
matches actual dds bus data width and saves bram
2015-06-20 23:53:01 -06:00
f47c2e54e1 DDS monitor fixes 2015-06-19 17:36:46 -06:00
5a9bdb2e33 DDS monitoring 2015-06-19 15:30:17 -06:00
Florent Kermarrec
38a0f63bd2 gateware/soc: use Minicon SDRAM controller and 128KB shared L2 cache 2015-06-18 12:18:03 +02:00
b2af0f6cc3 soc,runtime: support TTL override 2015-06-09 19:51:02 +08:00
a2ae5e4706 runtime: report TTL status over UDP 2015-06-03 18:26:19 +08:00
b81151eb42 soc: rtio monitor 2015-06-02 17:41:40 +08:00
cbb5027343 gateware/ad9858: use WaitTimer from Migen 2015-05-14 00:16:15 +08:00
a36c51eb83 DDS over RTIO (batch mode not supported yet) 2015-05-08 14:44:39 +08:00
a91bb48ced gateware: adapt to misoc changes 2015-05-06 18:02:15 +08:00
9072647bdc ad9858: make read timing configurable, increase read delays 2015-05-05 19:33:34 +08:00
cb65b1e322 rtio/phy/ttl_simple: reset sensitivity with RTIO logic 2015-05-02 16:17:31 +08:00
a61d701d47 rtio: decouple PHY reset from logic reset 2015-05-02 11:47:11 +08:00
62669f9ff2 soc: factor timer, kernel CPU and mailbox 2015-05-01 18:51:24 +08:00
9ecbb4c88d gateware/amp/mailbox: simplify 2015-04-29 12:56:21 +08:00
27d94a22de rtio: expose full_ts_width instead of counter_width parameter 2015-04-28 01:38:11 +08:00
e4251c7f41 runtime: get lwip to run 2015-04-22 15:01:32 +08:00
546996f896 coredevice,runtime: put ref_period into the ddb 2015-04-16 15:15:38 +08:00
71167b8adf rtio: do not attempt latency compensation in gateware 2015-04-16 13:09:29 +08:00
6215d63491 rtio: do not create spurious CSRs when data_width/address_width is 0 2015-04-16 13:04:19 +08:00
26003781b4 rtio/rtlink: add 'like' methods to clone interfaces 2015-04-16 13:02:39 +08:00
30dffb6644 rtio/phy: add wishbone adapter 2015-04-15 20:39:40 +08:00
4c10182c9f rtio: refactor, use rtlink 2015-04-14 19:44:45 +08:00
ff9a7727d2 rtio: add rtlink definition (currently unused) 2015-04-13 22:19:18 +08:00
7e591bb1c7 targets: use _Peripherals/UP/AMP class names, share QC1 IO defs 2015-04-07 00:07:53 +08:00
1ed60e0829 gateware/amp: use new ModuleTransformer API 2015-04-06 23:54:53 +08:00
c6d3750076 runtime,amp: set kernel memory start to SDRAM+128K, use custom linker file to split memory 2015-04-03 16:03:38 +08:00
Florent Kermarrec
2995f0a705 remove use of _r prefix on CSRs 2015-04-02 18:30:44 +08:00
5bd8d414cf gateware/amp: add kernel CPU and mailbox modules 2015-04-02 16:49:36 +08:00
3122623c6f rtio: make 63-bit timestamp counter the default [soc] 2015-03-12 13:13:35 +01:00
28bce9ee40 artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00