mirror of https://github.com/m-labs/artiq.git
drtio: use BlindTransfer for error reporting
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parent
8c414cebc7
commit
db3118b916
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@ -1,9 +1,10 @@
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"""Protocol error reporting for satellites."""
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from migen import *
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from migen.genlib.cdc import PulseSynchronizer
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from misoc.interconnect.csr import *
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from artiq.gateware.rtio.cdc import BlindTransfer
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class RTErrorsSatellite(Module, AutoCSR):
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def __init__(self, rt_packet, ios):
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@ -13,12 +14,12 @@ class RTErrorsSatellite(Module, AutoCSR):
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def error_csr(csr, *sources):
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for n, source in enumerate(sources):
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pending = Signal(related=source)
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ps = PulseSynchronizer("rtio", "sys")
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self.submodules += ps
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self.comb += ps.i.eq(source)
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xfer = BlindTransfer(odomain="sys")
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self.submodules += xfer
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self.comb += xfer.i.eq(source)
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self.sync += [
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If(csr.re & csr.r[n], pending.eq(0)),
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If(ps.o, pending.eq(1))
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If(xfer.o, pending.eq(1))
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]
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self.comb += csr.w[n].eq(pending)
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@ -5,7 +5,7 @@ from migen.genlib.fsm import *
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from migen.genlib.fifo import AsyncFIFO
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from migen.genlib.cdc import PulseSynchronizer
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from artiq.gateware.rtio.cdc import GrayCodeTransfer
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from artiq.gateware.rtio.cdc import GrayCodeTransfer, BlindTransfer
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from artiq.gateware.drtio.rt_serializer import *
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@ -252,8 +252,8 @@ class RTPacketMaster(Module):
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read_timestamp.eq(rx_dp.packet_as["read_reply"].timestamp)
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]
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err_unknown_packet_type = PulseSynchronizer("rtio_rx", "sys")
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err_packet_truncated = PulseSynchronizer("rtio_rx", "sys")
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err_unknown_packet_type = BlindTransfer("rtio_rx", "sys")
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err_packet_truncated = BlindTransfer("rtio_rx", "sys")
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self.submodules += err_unknown_packet_type, err_packet_truncated
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self.comb += [
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self.err_unknown_packet_type.eq(err_unknown_packet_type.o),
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@ -47,15 +47,16 @@ class RTIOCounter(Module):
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class BlindTransfer(Module):
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def __init__(self):
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def __init__(self, idomain="rio", odomain="rsys"):
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self.i = Signal()
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self.o = Signal()
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ps = PulseSynchronizer("rio", "rsys")
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ps_ack = PulseSynchronizer("rsys", "rio")
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ps = PulseSynchronizer(idomain, odomain)
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ps_ack = PulseSynchronizer(odomain, idomain)
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self.submodules += ps, ps_ack
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blind = Signal()
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self.sync.rio += [
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isync = getattr(self.sync, idomain)
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isync += [
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If(self.i, blind.eq(1)),
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If(ps_ack.o, blind.eq(0))
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]
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