Revert "drtio: order resets wrt writes"

This reverts commit 9a048c2b3a.
This commit is contained in:
Sebastien Bourdeauducq 2016-12-12 17:49:07 +08:00
parent 6a60afcba0
commit 4c59c0fecf
2 changed files with 32 additions and 43 deletions

View File

@ -57,6 +57,19 @@ class RTController(Module):
If(self.csrs.set_time.re, rt_packets.set_time_stb.eq(1))
]
# reset
self.sync += [
If(rt_packets.reset_ack, rt_packets.reset_stb.eq(0)),
If(self.csrs.reset.re,
rt_packets.reset_stb.eq(1),
rt_packets.reset_phy.eq(0)
),
If(self.csrs.reset_phy.re,
rt_packets.reset_stb.eq(1),
rt_packets.reset_phy.eq(1)
),
]
# remote channel status cache
fifo_spaces_mem = Memory(16, channel_count)
fifo_spaces = fifo_spaces_mem.get_port(write_capable=True)
@ -67,8 +80,6 @@ class RTController(Module):
# common packet fields
rt_packets_fifo_request = Signal()
rt_packets_reset_request = Signal()
rt_packets_reset_phy_request = Signal()
self.comb += [
fifo_spaces.adr.eq(chan_sel),
last_timestamps.adr.eq(chan_sel),
@ -78,10 +89,6 @@ class RTController(Module):
rt_packets.write_data.eq(self.cri.o_data),
If(rt_packets_fifo_request,
rt_packets.write_timestamp.eq(0xffff000000000000)
).Elif(rt_packets_reset_request,
rt_packets.write_timestamp.eq(0xffff000000000001)
).Elif(rt_packets_reset_phy_request,
rt_packets.write_timestamp.eq(0xffff000000000003)
).Else(
rt_packets.write_timestamp.eq(self.cri.o_timestamp)
)
@ -138,12 +145,6 @@ class RTController(Module):
),
If(self.csrs.o_get_fifo_space.re,
NextState("GET_FIFO_SPACE")
),
If(self.csrs.reset.re,
NextState("RESET")
),
If(self.csrs.reset_phy.re,
NextState("RESET_PHY")
)
)
fsm.act("WRITE",
@ -190,22 +191,6 @@ class RTController(Module):
NextState("IDLE")
)
)
fsm.act("RESET",
status_wait.eq(1),
rt_packets_reset_request.eq(1),
rt_packets.write_stb.eq(1),
If(rt_packets.write_ack,
NextState("IDLE")
)
)
fsm.act("RESET_PHY",
status_wait.eq(1),
rt_packets_reset_phy_request.eq(1),
rt_packets.write_stb.eq(1),
If(rt_packets.write_ack,
NextState("IDLE")
)
)
# channel state access
self.comb += [

View File

@ -430,8 +430,6 @@ class RTPacketMaster(Module):
# all interface signals in sys domain unless otherwise specified
# write interface, optimized for throughput
# writes, fifo space requests, and reset requests need to be ordered
# and all use the same FIFO.
self.write_stb = Signal()
self.write_ack = Signal()
self.write_timestamp = Signal(64)
@ -440,16 +438,12 @@ class RTPacketMaster(Module):
self.write_data = Signal(512)
# fifo space interface
# write with timestamp[48:] == 0xffff and timestamp[0] == 0
# to make a fifo space request
# write with timestamp[48:] == 0xffff to make a fifo space request
# (space requests have to be ordered wrt writes)
self.fifo_space_not = Signal()
self.fifo_space_not_ack = Signal()
self.fifo_space = Signal(16)
# reset interface
# write with timestamp[48:] == 0xffff, timestamp[0] == 1,
# and timestamp[1] == phy to make a reset request
# echo interface
self.echo_stb = Signal()
self.echo_ack = Signal()
@ -463,6 +457,11 @@ class RTPacketMaster(Module):
# a set_time request pending
self.tsc_value = Signal(64)
# reset interface
self.reset_stb = Signal()
self.reset_ack = Signal()
self.reset_phy = Signal()
# errors
self.error_not = Signal()
self.error_not_ack = Signal()
@ -566,6 +565,13 @@ class RTPacketMaster(Module):
self.set_time_stb, self.set_time_ack, None,
set_time_stb, set_time_ack, None)
reset_stb = Signal()
reset_ack = Signal()
reset_phy = Signal()
self.submodules += _CrossDomainRequest("rtio",
self.reset_stb, self.reset_ack, self.reset_phy,
reset_stb, reset_ack, reset_phy)
echo_stb = Signal()
echo_ack = Signal()
self.submodules += _CrossDomainRequest("rtio",
@ -591,11 +597,7 @@ class RTPacketMaster(Module):
tx_fsm.act("IDLE",
If(wfb_readable,
If(write_timestamp[48:] == 0xffff,
If(write_timestamp[0] == 0,
NextState("FIFO_SPACE")
).Else(
NextState("RESET")
)
NextState("FIFO_SPACE")
).Else(
NextState("WRITE")
)
@ -606,6 +608,8 @@ class RTPacketMaster(Module):
).Elif(set_time_stb,
tsc_value_load.eq(1),
NextState("SET_TIME")
).Elif(reset_stb,
NextState("RESET")
)
)
)
@ -655,9 +659,9 @@ class RTPacketMaster(Module):
)
)
tx_fsm.act("RESET",
tx_dp.send("reset", phy=write_timestamp[1]),
tx_dp.send("reset", phy=reset_phy),
If(tx_dp.packet_last,
wfb_re.eq(1),
reset_ack.eq(1),
NextState("IDLE")
)
)