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drtio: allow specifying 7series RXSynchronizer initial phase

This commit is contained in:
Sebastien Bourdeauducq 2016-11-08 16:52:40 +08:00
parent bcb5053fb6
commit 95acc9b9d4
1 changed files with 2 additions and 1 deletions
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3
artiq/gateware/drtio/transceiver/gtx_7series.py
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@ -208,7 +208,7 @@ class RXSynchronizer(Module, AutoCSR):
Xilinx scriptures (when existent) and should be constant for a given design
placement.
"""
def __init__(self, rtio_clk_freq):
def __init__(self, rtio_clk_freq, initial_phase=0.0):
self.phase_shift = CSR()
self.phase_shift_done = CSRStatus()
@ -228,6 +228,7 @@ class RXSynchronizer(Module, AutoCSR):
p_CLKFBOUT_MULT_F=mmcm_mult,
p_CLKOUT0_DIVIDE_F=mmcm_mult,
p_CLKOUT0_PHASE=intial_phase,
p_DIVCLK_DIVIDE=1,
# According to Xilinx, there is no guarantee of input/output