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gateware/serwb: for the initial version set delay in the center of the valid sampling window and don't use phase detectors
we'll use phase detectors later when it will be working reliably for both artix7 and kintex ultrascale
This commit is contained in:
Florent Kermarrec
parent
26a11a296c
commit
89558e2653
@ -5,8 +5,6 @@ from migen.genlib.misc import BitSlip
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from misoc.cores.code_8b10b import Encoder, Decoder
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from artiq.gateware.serwb.phy import PhaseDetector
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class KUSSerdesPLL(Module):
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def __init__(self, refclk_freq, linerate, vco_div=1):
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@ -228,22 +226,17 @@ class KUSSerdes(Module):
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self.submodules.rx_gearbox = Gearbox(8, "serdes_5x", 40, "serdes")
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self.submodules.rx_bitslip = ClockDomainsRenamer("serdes")(BitSlip(40))
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self.submodules.phase_detector = ClockDomainsRenamer("serdes_5x")(PhaseDetector())
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# 2 serdes for phase detection: 1 master (used for data) / 1 slave
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serdes_m_i_nodelay = Signal()
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serdes_s_i_nodelay = Signal()
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serdes_i_nodelay = Signal()
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self.specials += [
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Instance("IBUFDS_DIFF_OUT",
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i_I=pads.rx_p,
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i_IB=pads.rx_n,
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o_O=serdes_m_i_nodelay,
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o_OB=serdes_s_i_nodelay
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o_O=serdes_i_nodelay
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)
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]
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serdes_m_i_delayed = Signal()
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serdes_m_q = Signal(8)
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serdes_i_delayed = Signal()
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serdes_q = Signal(8)
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self.specials += [
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Instance("IDELAYE3",
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p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=200.0,
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@ -256,55 +249,22 @@ class KUSSerdes(Module):
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i_INC=rx_delay_inc, i_EN_VTC=rx_delay_en_vtc,
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i_CE=rx_delay_ce,
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i_IDATAIN=serdes_m_i_nodelay, o_DATAOUT=serdes_m_i_delayed
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i_IDATAIN=serdes_i_nodelay, o_DATAOUT=serdes_i_delayed
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),
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Instance("ISERDESE3",
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p_DATA_WIDTH=8,
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i_D=serdes_m_i_delayed,
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i_D=serdes_i_delayed,
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i_RST=ResetSignal("serdes"),
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i_FIFO_RD_CLK=0, i_FIFO_RD_EN=0,
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i_CLK=ClockSignal("serdes_20x"), i_CLK_B=~ClockSignal("serdes_20x"),
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i_CLKDIV=ClockSignal("serdes_5x"),
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o_Q=serdes_m_q
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o_Q=serdes_q
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)
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]
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self.comb += self.phase_detector.mdata.eq(serdes_m_q)
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serdes_s_i_delayed = Signal()
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serdes_s_q = Signal(8)
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self.specials += [
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Instance("IDELAYE3",
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p_CASCADE="NONE", p_UPDATE_MODE="ASYNC", p_REFCLK_FREQUENCY=200.0,
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p_IS_CLK_INVERTED=0, p_IS_RST_INVERTED=0,
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# Note: can't use TIME mode since not reloading DELAY_VALUE on rst...
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# Got answer from Xilinx, need testing:
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# https://forums.xilinx.com/xlnx/board/crawl_message?board.id=ultrascale&message.id=4699
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p_DELAY_FORMAT="COUNT", p_DELAY_SRC="IDATAIN",
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p_DELAY_TYPE="VARIABLE", p_DELAY_VALUE=50, # 1/4 bit period (ambient temp)
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i_CLK=ClockSignal("serdes_5x"),
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i_RST=rx_delay_rst, i_LOAD=0,
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i_INC=rx_delay_inc, i_EN_VTC=rx_delay_en_vtc,
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i_CE=rx_delay_ce,
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i_IDATAIN=serdes_s_i_nodelay, o_DATAOUT=serdes_s_i_delayed
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),
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Instance("ISERDESE3",
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p_DATA_WIDTH=8,
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i_D=serdes_s_i_delayed,
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i_RST=ResetSignal("serdes"),
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i_FIFO_RD_CLK=0, i_FIFO_RD_EN=0,
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i_CLK=ClockSignal("serdes_20x"), i_CLK_B=~ClockSignal("serdes_20x"),
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i_CLKDIV=ClockSignal("serdes_5x"),
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o_Q=serdes_s_q
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)
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]
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self.comb += self.phase_detector.sdata.eq(~serdes_s_q)
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self.comb += [
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self.rx_gearbox.i.eq(serdes_m_q),
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self.rx_gearbox.i.eq(serdes_q),
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self.rx_bitslip.value.eq(rx_bitslip_value),
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self.rx_bitslip.i.eq(self.rx_gearbox.o),
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self.decoders[0].input.eq(self.rx_bitslip.o[0:10]),
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@ -5,86 +5,6 @@ from migen.genlib.misc import WaitTimer
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from misoc.interconnect.csr import *
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class PhaseDetector(Module, AutoCSR):
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def __init__(self, nbits=8):
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self.mdata = Signal(8)
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self.sdata = Signal(8)
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self.reset = Signal()
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self.too_early = Signal()
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self.too_late = Signal()
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# # #
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# Ideal sampling (middle of the eye):
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# _____ _____ _____
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# | |_____| |_____| |_____| data
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# + + + + + + master sampling
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# - - - - - - slave sampling (90°/bit period)
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# Since taps are fixed length delays, this ideal case is not possible
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# and we will fall in the 2 following possible cases:
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#
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# 1) too late sampling (idelay needs to be decremented):
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# _____ _____ _____
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# | |_____| |_____| |_____| data
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# + + + + + + master sampling
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# - - - - - - slave sampling (90°/bit period)
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# On mdata transition, mdata != sdata
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#
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#
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# 2) too early sampling (idelay needs to be incremented):
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# _____ _____ _____
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# | |_____| |_____| |_____| data
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# + + + + + + master sampling
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# - - - - - - slave sampling (90°/bit period)
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# On mdata transition, mdata == sdata
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transition = Signal()
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inc = Signal()
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dec = Signal()
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# Find transition
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mdata_d = Signal(8)
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self.sync.serdes_5x += mdata_d.eq(self.mdata)
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self.comb += transition.eq(mdata_d != self.mdata)
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# Find what to do
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self.comb += [
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inc.eq(transition & (self.mdata == self.sdata)),
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dec.eq(transition & (self.mdata != self.sdata))
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]
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# Error accumulator
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lateness = Signal(nbits, reset=2**(nbits - 1))
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too_late = Signal()
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too_early = Signal()
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reset_lateness = Signal()
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self.comb += [
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too_late.eq(lateness == (2**nbits - 1)),
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too_early.eq(lateness == 0)
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]
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self.sync.serdes_5x += [
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If(reset_lateness,
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lateness.eq(2**(nbits - 1))
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).Elif(~too_late & ~too_early,
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If(inc, lateness.eq(lateness - 1)),
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If(dec, lateness.eq(lateness + 1))
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)
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]
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# control / status cdc
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self.specials += [
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MultiReg(too_early, self.too_early),
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MultiReg(too_late, self.too_late)
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]
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self.submodules.do_reset_lateness = PulseSynchronizer("sys", "serdes_5x")
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self.comb += [
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reset_lateness.eq(self.do_reset_lateness.o),
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self.do_reset_lateness.i.eq(self.reset)
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]
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# Master <--> Slave synchronization:
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# 1) Master sends idle pattern (zeroes) to reset Slave.
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# 2) Master sends K28.5 commas to allow Slave to calibrate, Slave sends idle pattern.
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@ -102,25 +22,26 @@ class SerdesMasterInit(Module):
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# # #
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self.delay = delay = Signal(max=taps)
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self.delay_found = delay_found = Signal()
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self.delay_min = delay_min = Signal(max=taps)
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self.delay_min_found = delay_min_found = Signal()
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self.delay_max = delay_max = Signal(max=taps)
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self.delay_max_found = delay_max_found = Signal()
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self.bitslip = bitslip = Signal(max=40)
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self.bitslip_found = bitslip_found = Signal()
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timer = WaitTimer(8192)
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timer = WaitTimer(1024)
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self.submodules += timer
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
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self.comb += self.fsm.reset.eq(self.reset)
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phase_detector_too_early_last = Signal()
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fsm.act("IDLE",
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NextValue(delay_found, 0),
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NextValue(delay, 0),
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NextValue(delay_min, 0),
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NextValue(delay_min_found, 0),
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NextValue(delay_max, 0),
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NextValue(delay_max_found, 0),
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serdes.rx_delay_rst.eq(1),
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NextValue(bitslip_found, 0),
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NextValue(bitslip, 0),
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NextValue(phase_detector_too_early_last, 0),
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NextState("RESET_SLAVE"),
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serdes.tx_idle.eq(1)
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)
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@ -142,61 +63,75 @@ class SerdesMasterInit(Module):
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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serdes.phase_detector.reset.eq(1),
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If(~delay_found,
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NextState("CHECK_PHASE")
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).Else(
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NextState("CHECK_PATTERN")
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),
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("CHECK_PHASE",
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# Since we are always incrementing delay,
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# ideal sampling is found when phase detector
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# transitions from too_early to too_late
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If(serdes.phase_detector.too_late &
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phase_detector_too_early_last,
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NextValue(delay_found, 1),
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NextState("CHECK_PATTERN")
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).Elif(serdes.phase_detector.too_late |
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serdes.phase_detector.too_early,
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NextValue(phase_detector_too_early_last,
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serdes.phase_detector.too_early),
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NextState("INC_DELAY")
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("INC_DELAY",
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If(delay == (taps - 1),
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NextState("ERROR")
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1),
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serdes.rx_delay_ce.eq(1),
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NextState("WAIT_STABLE")
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("CHECK_PATTERN",
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If(serdes.rx_comma,
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timer.wait.eq(1),
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If(timer.done,
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NextValue(bitslip_found, 1),
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NextState("READY")
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)
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If(~delay_min_found,
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If(serdes.rx_comma,
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timer.wait.eq(1),
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If(timer.done,
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NextValue(delay_min, delay),
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NextValue(delay_min_found, 1)
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)
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).Else(
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NextState("INC_DELAY_BITSLIP")
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),
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).Else(
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NextState("INC_BITSLIP")
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If(~serdes.rx_comma,
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NextValue(delay_max, delay),
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NextValue(delay_max_found, 1),
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NextState("RESET_SAMPLING_WINDOW")
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).Else(
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NextState("INC_DELAY_BITSLIP")
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)
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),
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serdes.tx_comma.eq(1)
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)
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self.comb += serdes.rx_bitslip_value.eq(bitslip)
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fsm.act("INC_BITSLIP",
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If(bitslip == (40 - 1),
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NextState("ERROR")
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fsm.act("INC_DELAY_BITSLIP",
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NextState("WAIT_STABLE"),
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If(delay == (taps - 1),
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If(delay_min_found,
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NextState("ERROR")
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),
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If(bitslip == (40 - 1),
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NextValue(bitslip, 0)
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).Else(
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NextValue(bitslip, bitslip + 1)
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),
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1)
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).Else(
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NextValue(bitslip, bitslip + 1),
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NextState("WAIT_STABLE")
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1),
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serdes.rx_delay_ce.eq(1)
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("RESET_SAMPLING_WINDOW",
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NextValue(delay, 0),
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serdes.rx_delay_rst.eq(1),
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NextState("WAIT_SAMPLING_WINDOW"),
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serdes.tx_comma.eq(1)
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)
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fsm.act("CONFIGURE_SAMPLING_WINDOW",
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If(delay == (delay_min + (delay_max - delay_min)[1:]),
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NextState("READY")
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1),
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serdes.rx_delay_ce.eq(1),
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NextState("WAIT_SAMPLING_WINDOW")
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),
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serdes.tx_comma.eq(1)
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)
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fsm.act("WAIT_SAMPLING_WINDOW",
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextState("CONFIGURE_SAMPLING_WINDOW")
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),
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serdes.tx_comma.eq(1)
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)
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@ -217,9 +152,11 @@ class SerdesSlaveInit(Module, AutoCSR):
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# # #
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self.delay = delay = Signal(max=taps)
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self.delay_found = delay_found = Signal()
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self.delay_min = delay_min = Signal(max=taps)
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self.delay_min_found = delay_min_found = Signal()
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self.delay_max = delay_max = Signal(max=taps)
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self.delay_max_found = delay_max_found = Signal()
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self.bitslip = bitslip = Signal(max=40)
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self.bitslip_found = bitslip_found = Signal()
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timer = WaitTimer(1024)
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self.submodules += timer
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@ -227,16 +164,14 @@ class SerdesSlaveInit(Module, AutoCSR):
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self.comb += self.reset.eq(serdes.rx_idle)
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self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="IDLE"))
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phase_detector_too_early_last = Signal()
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fsm.act("IDLE",
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NextValue(delay_found, 0),
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NextValue(delay, 0),
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NextValue(delay_min, 0),
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NextValue(delay_min_found, 0),
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NextValue(delay_max, 0),
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NextValue(delay_max_found, 0),
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serdes.rx_delay_rst.eq(1),
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NextValue(bitslip_found, 0),
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NextValue(bitslip, 0),
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NextValue(phase_detector_too_early_last, 0),
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NextState("WAIT_STABLE"),
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serdes.tx_idle.eq(1)
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)
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@ -244,64 +179,76 @@ class SerdesSlaveInit(Module, AutoCSR):
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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serdes.phase_detector.reset.eq(1),
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If(~delay_found,
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NextState("CHECK_PHASE")
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).Else(
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NextState("CHECK_PATTERN")
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),
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("CHECK_PHASE",
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# Since we are always incrementing delay,
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# ideal sampling is found when phase detector
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# transitions from too_early to too_late
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If(serdes.phase_detector.too_late &
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phase_detector_too_early_last,
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NextValue(delay_found, 1),
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NextState("CHECK_PATTERN")
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).Elif(serdes.phase_detector.too_late |
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serdes.phase_detector.too_early,
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NextValue(phase_detector_too_early_last,
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serdes.phase_detector.too_early),
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NextState("INC_DELAY")
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("INC_DELAY",
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If(delay == (taps - 1),
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NextState("ERROR")
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).Else(
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NextValue(delay, delay + 1),
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serdes.rx_delay_inc.eq(1),
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serdes.rx_delay_ce.eq(1),
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NextState("WAIT_STABLE")
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),
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serdes.tx_idle.eq(1)
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)
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fsm.act("CHECK_PATTERN",
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If(serdes.rx_comma,
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timer.wait.eq(1),
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If(timer.done,
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NextValue(bitslip_found, 1),
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NextState("SEND_PATTERN")
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)
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If(~delay_min_found,
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If(serdes.rx_comma,
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timer.wait.eq(1),
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If(timer.done,
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timer.wait.eq(0),
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NextValue(delay_min, delay),
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NextValue(delay_min_found, 1)
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)
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).Else(
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NextState("INC_DELAY_BITSLIP")
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),
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).Else(
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NextState("INC_BITSLIP")
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If(~serdes.rx_comma,
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NextValue(delay_max, delay),
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NextValue(delay_max_found, 1),
|
||||
NextState("RESET_SAMPLING_WINDOW")
|
||||
).Else(
|
||||
NextState("INC_DELAY_BITSLIP")
|
||||
)
|
||||
),
|
||||
serdes.tx_idle.eq(1)
|
||||
)
|
||||
self.comb += serdes.rx_bitslip_value.eq(bitslip)
|
||||
fsm.act("INC_BITSLIP",
|
||||
If(bitslip == (40 - 1),
|
||||
NextState("ERROR")
|
||||
fsm.act("INC_DELAY_BITSLIP",
|
||||
NextState("WAIT_STABLE"),
|
||||
If(delay == (taps - 1),
|
||||
If(delay_min_found,
|
||||
NextState("ERROR")
|
||||
),
|
||||
If(bitslip == (40 - 1),
|
||||
NextValue(bitslip, 0)
|
||||
).Else(
|
||||
NextValue(bitslip, bitslip + 1)
|
||||
),
|
||||
NextValue(delay, 0),
|
||||
serdes.rx_delay_rst.eq(1)
|
||||
).Else(
|
||||
NextValue(bitslip, bitslip + 1),
|
||||
NextState("WAIT_STABLE")
|
||||
NextValue(delay, delay + 1),
|
||||
serdes.rx_delay_inc.eq(1),
|
||||
serdes.rx_delay_ce.eq(1)
|
||||
),
|
||||
serdes.tx_idle.eq(1)
|
||||
)
|
||||
fsm.act("RESET_SAMPLING_WINDOW",
|
||||
NextValue(delay, 0),
|
||||
serdes.rx_delay_rst.eq(1),
|
||||
NextState("WAIT_SAMPLING_WINDOW")
|
||||
)
|
||||
fsm.act("CONFIGURE_SAMPLING_WINDOW",
|
||||
If(delay == (delay_min + (delay_max - delay_min)[1:]),
|
||||
NextState("SEND_PATTERN")
|
||||
).Else(
|
||||
NextValue(delay, delay + 1),
|
||||
serdes.rx_delay_inc.eq(1),
|
||||
serdes.rx_delay_ce.eq(1),
|
||||
NextState("WAIT_SAMPLING_WINDOW")
|
||||
)
|
||||
)
|
||||
fsm.act("WAIT_SAMPLING_WINDOW",
|
||||
timer.wait.eq(1),
|
||||
If(timer.done,
|
||||
timer.wait.eq(0),
|
||||
NextState("CONFIGURE_SAMPLING_WINDOW")
|
||||
)
|
||||
)
|
||||
fsm.act("SEND_PATTERN",
|
||||
timer.wait.eq(1),
|
||||
If(timer.done,
|
||||
@ -327,9 +274,11 @@ class SerdesControl(Module, AutoCSR):
|
||||
self.error = CSRStatus()
|
||||
|
||||
self.delay = CSRStatus(9)
|
||||
self.delay_found = CSRStatus()
|
||||
self.delay_min_found = CSRStatus()
|
||||
self.delay_min = CSRStatus(9)
|
||||
self.delay_max_found = CSRStatus()
|
||||
self.delay_max = CSRStatus(9)
|
||||
self.bitslip = CSRStatus(6)
|
||||
self.bitslip_found = CSRStatus()
|
||||
|
||||
# # #
|
||||
|
||||
@ -338,8 +287,10 @@ class SerdesControl(Module, AutoCSR):
|
||||
self.comb += [
|
||||
self.ready.status.eq(init.ready),
|
||||
self.error.status.eq(init.error),
|
||||
self.delay_found.status.eq(init.delay_found),
|
||||
self.delay.status.eq(init.delay),
|
||||
self.bitslip_found.status.eq(init.bitslip_found),
|
||||
self.delay_min_found.status.eq(init.delay_min_found),
|
||||
self.delay_min.status.eq(init.delay_min),
|
||||
self.delay_max_found.status.eq(init.delay_max_found),
|
||||
self.delay_max.status.eq(init.delay_max),
|
||||
self.bitslip.status.eq(init.bitslip)
|
||||
]
|
||||
|
||||
@ -5,8 +5,6 @@ from migen.genlib.misc import BitSlip
|
||||
|
||||
from misoc.cores.code_8b10b import Encoder, Decoder
|
||||
|
||||
from artiq.gateware.serwb.phy import PhaseDetector
|
||||
|
||||
|
||||
class S7SerdesPLL(Module):
|
||||
def __init__(self, refclk_freq, linerate, vco_div=1):
|
||||
@ -221,22 +219,17 @@ class S7Serdes(Module):
|
||||
self.submodules.rx_gearbox = Gearbox(8, "serdes_5x", 40, "serdes")
|
||||
self.submodules.rx_bitslip = ClockDomainsRenamer("serdes")(BitSlip(40))
|
||||
|
||||
self.submodules.phase_detector = ClockDomainsRenamer("serdes_5x")(PhaseDetector())
|
||||
|
||||
# 2 serdes for phase detection: 1 master (used for data) / 1 slave
|
||||
serdes_m_i_nodelay = Signal()
|
||||
serdes_s_i_nodelay = Signal()
|
||||
serdes_i_nodelay = Signal()
|
||||
self.specials += [
|
||||
Instance("IBUFDS_DIFF_OUT",
|
||||
i_I=pads.rx_p,
|
||||
i_IB=pads.rx_n,
|
||||
o_O=serdes_m_i_nodelay,
|
||||
o_OB=serdes_s_i_nodelay
|
||||
o_O=serdes_i_nodelay
|
||||
)
|
||||
]
|
||||
|
||||
serdes_m_i_delayed = Signal()
|
||||
serdes_m_q = Signal(8)
|
||||
serdes_i_delayed = Signal()
|
||||
serdes_q = Signal(8)
|
||||
self.specials += [
|
||||
Instance("IDELAYE2",
|
||||
p_DELAY_SRC="IDATAIN", p_SIGNAL_PATTERN="DATA",
|
||||
@ -249,66 +242,28 @@ class S7Serdes(Module):
|
||||
i_CE=self.rx_delay_ce,
|
||||
i_LDPIPEEN=0, i_INC=self.rx_delay_inc,
|
||||
|
||||
i_IDATAIN=serdes_m_i_nodelay, o_DATAOUT=serdes_m_i_delayed
|
||||
i_IDATAIN=serdes_i_nodelay, o_DATAOUT=serdes_i_delayed
|
||||
),
|
||||
Instance("ISERDESE2",
|
||||
p_DATA_WIDTH=8, p_DATA_RATE="DDR",
|
||||
p_SERDES_MODE="MASTER", p_INTERFACE_TYPE="NETWORKING",
|
||||
p_NUM_CE=1, p_IOBDELAY="IFD",
|
||||
|
||||
i_DDLY=serdes_m_i_delayed,
|
||||
i_DDLY=serdes_i_delayed,
|
||||
i_CE1=1,
|
||||
i_RST=ResetSignal("serdes"),
|
||||
i_CLK=ClockSignal("serdes_20x"), i_CLKB=~ClockSignal("serdes_20x"),
|
||||
i_CLKDIV=ClockSignal("serdes_5x"),
|
||||
i_BITSLIP=0,
|
||||
o_Q8=serdes_m_q[0], o_Q7=serdes_m_q[1],
|
||||
o_Q6=serdes_m_q[2], o_Q5=serdes_m_q[3],
|
||||
o_Q4=serdes_m_q[4], o_Q3=serdes_m_q[5],
|
||||
o_Q2=serdes_m_q[6], o_Q1=serdes_m_q[7]
|
||||
o_Q8=serdes_q[0], o_Q7=serdes_q[1],
|
||||
o_Q6=serdes_q[2], o_Q5=serdes_q[3],
|
||||
o_Q4=serdes_q[4], o_Q3=serdes_q[5],
|
||||
o_Q2=serdes_q[6], o_Q1=serdes_q[7]
|
||||
)
|
||||
]
|
||||
self.comb += self.phase_detector.mdata.eq(serdes_m_q)
|
||||
|
||||
serdes_s_i_delayed = Signal()
|
||||
serdes_s_q = Signal(8)
|
||||
serdes_s_idelay_value = int(1/(4*pll.linerate)/78e-12) # 1/4 bit period
|
||||
assert serdes_s_idelay_value < 32
|
||||
self.specials += [
|
||||
Instance("IDELAYE2",
|
||||
p_DELAY_SRC="IDATAIN", p_SIGNAL_PATTERN="DATA",
|
||||
p_CINVCTRL_SEL="FALSE", p_HIGH_PERFORMANCE_MODE="TRUE",
|
||||
p_REFCLK_FREQUENCY=200.0, p_PIPE_SEL="FALSE",
|
||||
p_IDELAY_TYPE="VARIABLE", p_IDELAY_VALUE=serdes_s_idelay_value,
|
||||
|
||||
i_C=ClockSignal(),
|
||||
i_LD=self.rx_delay_rst,
|
||||
i_CE=self.rx_delay_ce,
|
||||
i_LDPIPEEN=0, i_INC=self.rx_delay_inc,
|
||||
|
||||
i_IDATAIN=serdes_s_i_nodelay, o_DATAOUT=serdes_s_i_delayed
|
||||
),
|
||||
Instance("ISERDESE2",
|
||||
p_DATA_WIDTH=8, p_DATA_RATE="DDR",
|
||||
p_SERDES_MODE="MASTER", p_INTERFACE_TYPE="NETWORKING",
|
||||
p_NUM_CE=1, p_IOBDELAY="IFD",
|
||||
|
||||
i_DDLY=serdes_s_i_delayed,
|
||||
i_CE1=1,
|
||||
i_RST=ResetSignal("serdes"),
|
||||
i_CLK=ClockSignal("serdes_20x"), i_CLKB=~ClockSignal("serdes_20x"),
|
||||
i_CLKDIV=ClockSignal("serdes_5x"),
|
||||
i_BITSLIP=0,
|
||||
o_Q8=serdes_s_q[0], o_Q7=serdes_s_q[1],
|
||||
o_Q6=serdes_s_q[2], o_Q5=serdes_s_q[3],
|
||||
o_Q4=serdes_s_q[4], o_Q3=serdes_s_q[5],
|
||||
o_Q2=serdes_s_q[6], o_Q1=serdes_s_q[7]
|
||||
)
|
||||
]
|
||||
self.comb += self.phase_detector.sdata.eq(~serdes_s_q)
|
||||
|
||||
self.comb += [
|
||||
self.rx_gearbox.i.eq(serdes_m_q),
|
||||
self.rx_gearbox.i.eq(serdes_q),
|
||||
self.rx_bitslip.value.eq(rx_bitslip_value),
|
||||
self.rx_bitslip.i.eq(self.rx_gearbox.o),
|
||||
self.decoders[0].input.eq(self.rx_bitslip.o[0:10]),
|
||||
|
||||
Loading…
Reference in New Issue
Block a user