mirror of https://github.com/m-labs/artiq.git
drtio: support for local RTIO core
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d37b73fd31
commit
c419c422fa
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@ -83,5 +83,66 @@
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"arguments": {"channel": 9}
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},
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"led0": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0x010000},
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},
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"led1": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0x010001},
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},
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"led2": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0x010002},
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},
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"led3": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0x010003},
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},
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"led4": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0x010004},
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},
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"led5": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0x010005},
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},
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"led6": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0x010006},
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},
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"led7": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0x010007},
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},
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"smap": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0x010008}
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},
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"sman": {
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"type": "local",
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"module": "artiq.coredevice.ttl",
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"class": "TTLOut",
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"arguments": {"channel": 0x010009}
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},
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}
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@ -4,17 +4,24 @@ from artiq.experiment import *
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class BlinkForever(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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self.leds = [self.get_device("rled" + str(i)) for i in range(8)]
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self.rleds = [self.get_device("rled" + str(i)) for i in range(8)]
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self.leds = [self.get_device("led" + str(i)) for i in range(8)]
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@kernel
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def run(self):
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self.core.reset()
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while True:
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for led in self.leds:
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led.pulse(250*ms)
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with parallel:
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for led in self.leds:
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led.pulse(250*ms)
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for led in self.rleds:
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led.pulse(250*ms)
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t = now_mu()
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for led in self.leds:
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at_mu(t)
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led.pulse(500*ms)
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for led in self.rleds:
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at_mu(t)
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led.pulse(500*ms)
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delay(250*ms)
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@ -1,4 +1,4 @@
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from artiq.gateware.rtio.cri import KernelInitiator
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from artiq.gateware.rtio.cri import KernelInitiator, CRIDecoder
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from artiq.gateware.rtio.core import Channel, LogChannel, Core
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from artiq.gateware.rtio.analyzer import Analyzer
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from artiq.gateware.rtio.moninj import MonInj
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@ -116,3 +116,34 @@ class KernelInitiator(Module, AutoCSR):
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self.o_data.we.eq(self.o_timestamp.re),
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]
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self.sync += If(self.counter_update.re, self.counter.status.eq(self.cri.counter))
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class CRIDecoder(Module):
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def __init__(self, slaves=2, master=None):
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if isinstance(slaves, int):
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slaves = [Interface() for _ in range(slaves)]
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if master is None:
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master = Interface()
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self.slaves = slaves
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self.master = master
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# # #
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selected = Signal(8)
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self.sync += selected.eq(self.master.chan_sel[16:])
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# master -> slave
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for n, slave in enumerate(slaves):
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for name, size, direction in _layout:
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if direction == DIR_M_TO_S and name != "cmd":
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self.comb += getattr(slave, name).eq(getattr(master, name))
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self.comb += If(selected == n, slave.cmd.eq(master.cmd))
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# slave -> master
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cases = dict()
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for n, slave in enumerate(slaves):
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cases[n] = []
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for name, size, direction in _layout:
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if direction == DIR_S_TO_M:
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cases[n].append(getattr(master, name).eq(getattr(slave, name)))
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self.comb += Case(selected, cases)
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@ -9,6 +9,7 @@ from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.soc import AMPSoC, build_artiq_soc
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio import DRTIOMaster
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from artiq import __version__ as artiq_version
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@ -42,10 +43,23 @@ class Master(MiniSoC, AMPSoC):
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sys_clk_freq=self.clk_freq,
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clock_div2=True)
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self.submodules.drtio = DRTIOMaster(self.transceiver)
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self.submodules.rtio = rtio.KernelInitiator(self.drtio.cri)
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self.register_kernel_cpu_csrdevice("rtio")
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self.csr_devices.append("drtio")
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rtio_channels = []
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for i in range(8):
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phy = ttl_simple.Output(platform.request("user_led", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for sma in "user_sma_gpio_p", "user_sma_gpio_n":
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phy = ttl_simple.Inout(platform.request(sma))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.submodules.cridec = rtio.CRIDecoder([self.drtio.cri, self.rtio_core.cri])
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self.submodules.rtio = rtio.KernelInitiator(self.cridec.cri)
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self.register_kernel_cpu_csrdevice("rtio")
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def main():
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parser = argparse.ArgumentParser(
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