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mirror of https://github.com/m-labs/artiq.git synced 2024-12-12 21:26:37 +08:00
artiq/artiq/gateware
2016-10-06 16:21:15 +02:00
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amp Implement core device storage (fixes #219). 2016-01-10 13:04:55 +00:00
dsp phaser: add jesd204b rtio dds 2016-10-05 16:17:50 +02:00
rtio phaser: add jesd204b rtio dds 2016-10-05 16:17:50 +02:00
targets ad9154: merge csr spaces 2016-10-06 16:21:15 +02:00
__init__.py artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
ad9xxx.py gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
nist_clock.py gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
nist_qc1.py gateware,runtime: use new migen/misoc 2015-11-04 00:35:03 +08:00
nist_qc2.py qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00
phaser.py phaser: add jesd204b rtio dds 2016-10-05 16:17:50 +02:00
soc.py gateware: use new misoc CSR mapping API 2016-09-24 20:48:37 +08:00
spi.py spi: use misoc SPIMachine, closes #314 2016-08-26 14:08:12 +02:00