M-Labs
/
artiq
mirror of https://github.com/m-labs/artiq.git
2
0
Fork 1
Code Issues Projects Releases Wiki Activity

phaser: drive rtio from jesd-bufg

This commit is contained in:
Robert Jördens 2016-10-14 02:26:19 +02:00
parent b9de621557
commit 3c9c42c779
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
artiq/gateware/targets/kc705.py
View File

@ -567,7 +567,7 @@ class Phaser(_NIST_Ions):
rtio_channels.append(rtio.LogChannel())
self.add_rtio(rtio_channels, _PhaserCRG(platform, self.crg.cd_sys.clk))
self.comb += self.rtio_crg.refclk.eq(self.ad9154.jesd.refclk)
self.comb += self.rtio_crg.refclk.eq(self.ad9154.jesd.cd_jesd.clk)
def main():