mirror of https://github.com/m-labs/artiq.git
drtio: initialize si5324 in firmware
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parent
3488b4a857
commit
f512ea42dc
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@ -8,6 +8,28 @@ extern crate log;
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extern crate logger_artiq;
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extern crate board;
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#[cfg(rtio_frequency = "62.5")]
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const SI5324_SETTINGS: board::si5324::FrequencySettings
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= board::si5324::FrequencySettings {
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n1_hs : 10,
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nc1_ls : 8,
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n2_hs : 10,
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n2_ls : 20112,
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n31 : 2514,
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n32 : 4597
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};
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#[cfg(rtio_frequency = "150.0")]
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const SI5324_SETTINGS: board::si5324::FrequencySettings
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= board::si5324::FrequencySettings {
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n1_hs : 9,
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nc1_ls : 4,
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n2_hs : 10,
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n2_ls : 33732,
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n31 : 9370,
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n32 : 7139
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};
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fn startup() {
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board::clock::init();
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info!("ARTIQ satellite manager starting...");
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@ -16,6 +38,8 @@ fn startup() {
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#[cfg(has_ad9516)]
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board::ad9516::init().expect("cannot initialize ad9516");
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board::i2c::init();
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board::si5324::setup_hitless_clock_switching(&SI5324_SETTINGS).expect("cannot initialize si5324");
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loop {}
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}
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@ -3,9 +3,8 @@ import os
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from migen import *
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from migen.build.generic_platform import *
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from misoc.cores.i2c import *
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from misoc.cores.sequencer import *
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from misoc.cores import spi as spi_csr
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from misoc.cores import gpio
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from misoc.integration.builder import *
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from misoc.integration.soc_core import mem_decoder
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from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
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@ -19,119 +18,6 @@ from artiq import __version__ as artiq_version
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from artiq import __artiq_dir__ as artiq_dir
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# NOTE: the logical parameters DO NOT MAP to physical values written
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# into registers. They have to be mapped; see the datasheet.
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# DSPLLsim reports the logical parameters in the design summary, not
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# the physical register values.
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pll_dividers_62_5 = {
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"N1_HS" : 6, # 10
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"NC1_LS" : 7, # 8
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"N2_HS" : 6, # 10
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"N2_LS" : 20111, # 20112
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"N31" : 2513, # 2514
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"N32" : 4596 # 4597
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}
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pll_dividers_150 = {
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"N1_HS" : 5, # 9
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"NC1_LS" : 3, # 4
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"N2_HS" : 6, # 10
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"N2_LS" : 33731, # 33732
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"N31" : 9369, # 9370
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"N32" : 7138 # 7139
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}
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# TODO: move I2C programming to softcore CPU
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def get_i2c_program(d, sys_clk_freq):
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i2c_sequence = [
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# PCA9548: select channel 7
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[(0x74 << 1), 1 << 7],
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# Si5324: configure
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[(0x68 << 1), 0, 0b01010000], # FREE_RUN=1
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[(0x68 << 1), 1, 0b11100100], # CK_PRIOR2=1 CK_PRIOR1=0
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[(0x68 << 1), 2, 0b0010 | (4 << 4)], # BWSEL=4
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[(0x68 << 1), 3, 0b0101 | 0x10], # SQ_ICAL=1
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[(0x68 << 1), 4, 0b10010010], # AUTOSEL_REG=b10
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[(0x68 << 1), 6, 0x07], # SFOUT1_REG=b111
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[(0x68 << 1), 25, (d["N1_HS"] << 5 ) & 0xff],
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[(0x68 << 1), 31, (d["NC1_LS"] >> 16) & 0xff],
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[(0x68 << 1), 32, (d["NC1_LS"] >> 8 ) & 0xff],
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[(0x68 << 1), 33, (d["NC1_LS"]) & 0xff],
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[(0x68 << 1), 40, (d["N2_HS"] << 5 ) & 0xff |
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(d["N2_LS"] >> 16) & 0xff],
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[(0x68 << 1), 41, (d["N2_LS"] >> 8 ) & 0xff],
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[(0x68 << 1), 42, (d["N2_LS"]) & 0xff],
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[(0x68 << 1), 43, (d["N31"] >> 16) & 0xff],
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[(0x68 << 1), 44, (d["N31"] >> 8) & 0xff],
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[(0x68 << 1), 45, (d["N31"]) & 0xff],
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[(0x68 << 1), 46, (d["N32"] >> 16) & 0xff],
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[(0x68 << 1), 47, (d["N32"] >> 8) & 0xff],
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[(0x68 << 1), 48, (d["N32"]) & 0xff],
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[(0x68 << 1), 137, 0x01], # FASTLOCK=1
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[(0x68 << 1), 136, 0x40], # ICAL=1
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]
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program = [
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InstWrite(I2C_CONFIG_ADDR, int(sys_clk_freq/1e3)),
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]
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for subseq in i2c_sequence:
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program += [
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InstWrite(I2C_XFER_ADDR, I2C_START),
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InstWait(I2C_XFER_ADDR, I2C_IDLE),
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]
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for octet in subseq:
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program += [
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InstWrite(I2C_XFER_ADDR, I2C_WRITE | octet),
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InstWait(I2C_XFER_ADDR, I2C_IDLE),
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]
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program += [
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InstWrite(I2C_XFER_ADDR, I2C_STOP),
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InstWait(I2C_XFER_ADDR, I2C_IDLE),
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]
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program += [
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InstEnd(),
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]
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return program
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class Si5324ResetClock(Module):
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def __init__(self, platform, sys_clk_freq):
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self.si5324_not_ready = Signal(reset=1)
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# minimum reset pulse 1us
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reset_done = Signal()
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si5324_rst_n = platform.request("si5324").rst_n
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reset_val = int(sys_clk_freq*1.1e-6)
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reset_ctr = Signal(max=reset_val+1, reset=reset_val)
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self.sync += \
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If(reset_ctr != 0,
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reset_ctr.eq(reset_ctr - 1)
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).Else(
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si5324_rst_n.eq(1),
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reset_done.eq(1)
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)
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# 10ms after reset to microprocessor access ready
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ready_val = int(sys_clk_freq*11e-3)
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ready_ctr = Signal(max=ready_val+1, reset=ready_val)
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self.sync += \
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If(reset_done,
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If(ready_ctr != 0,
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ready_ctr.eq(ready_ctr - 1)
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).Else(
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self.si5324_not_ready.eq(0)
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)
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)
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si5324_clkin = platform.request("si5324_clkin")
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self.specials += \
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Instance("OBUFDS",
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i_I=ClockSignal("rtio_rx"),
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o_O=si5324_clkin.p, o_OB=si5324_clkin.n
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)
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class Satellite(BaseSoC):
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mem_map = {
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"drtio_aux": 0x50000000,
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@ -158,22 +44,6 @@ class Satellite(BaseSoC):
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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if cfg == "simple_gbe":
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pll_dividers = pll_dividers_62_5
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elif cfg == "sawg_3g":
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pll_dividers = pll_dividers_150
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else:
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raise ValueError
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i2c_master = I2CMaster(platform.request("i2c"))
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sequencer = ResetInserter()(
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Sequencer(get_i2c_program(pll_dividers, self.clk_freq)))
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si5324_reset_clock = Si5324ResetClock(platform, self.clk_freq)
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self.submodules += i2c_master, sequencer, si5324_reset_clock
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self.comb += [
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sequencer.bus.connect(i2c_master.bus),
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sequencer.reset.eq(si5324_reset_clock.si5324_not_ready)
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]
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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tx_pads = platform.request("sfp_tx")
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rx_pads = platform.request("sfp_rx")
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@ -215,6 +85,19 @@ class Satellite(BaseSoC):
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self.drtio.aux_controller.bus)
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self.add_memory_region("drtio_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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self.config["RTIO_FREQUENCY"] = str(self.transceiver.rtio_clk_freq/1e6)
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si5324_clkin = platform.request("si5324_clkin")
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self.specials += \
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Instance("OBUFDS",
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i_I=ClockSignal("rtio_rx"),
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o_O=si5324_clkin.p, o_OB=si5324_clkin.n
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)
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self.comb += platform.request("si5324").rst_n.eq(1)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.csr_devices.append("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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rtio_clk_period = 1e9/self.transceiver.rtio_clk_freq
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platform.add_period_constraint(self.transceiver.txoutclk, rtio_clk_period)
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platform.add_period_constraint(self.transceiver.rxoutclk, rtio_clk_period)
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