mirror of https://github.com/m-labs/artiq.git
rtio: CRI arbiter (untested)
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@ -147,3 +147,47 @@ class CRIDecoder(Module):
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if direction == DIR_S_TO_M:
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cases[n].append(getattr(master, name).eq(getattr(slave, name)))
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self.comb += Case(selected, cases)
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class CRIArbiter(Module):
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def __init__(self, masters=2, slave=None):
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if isinstance(masters, int):
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masters = [Interface() for _ in range(masters)]
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if slave is None:
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slave = Interface()
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self.masters = masters
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self.slave = slave
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# # #
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selected = Signal(max=len(masters))
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# mux master->slave signals
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for name, size, direction in layout:
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if direction == DIR_M_TO_S:
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choices = Array(getattr(m, name) for m in masters)
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self.comb += getattr(slave, name).eq(choices[selected])
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# connect slave->master signals
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for name, size, direction in layout:
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if direction == DIR_S_TO_M:
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source = getattr(slave, name)
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for i, m in enumerate(masters):
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dest = getattr(m, name)
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if name == "arb_gnt":
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self.comb += dest.eq(source & (selected == i))
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else:
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self.comb += dest.eq(source)
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# select master
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self.sync += \
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If(~slave.arb_req,
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[If(m.arb_req, selected.eq(i)) for i, m in enumerate(masters)]
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)
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class CRIInterconnectShared(Module):
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def __init__(self, masters=2, slaves=2):
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shared = Interface()
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self.submodules.arbiter = CRIArbiter(masters, shared)
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self.submodules.decoder = CRIDecoder(slaves, shared)
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