mirror of https://github.com/m-labs/artiq.git
phaser: use Inout_8X
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@ -201,12 +201,12 @@ class Phaser(MiniSoC, AMPSoC):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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sysref_pads = platform.request("ad9154_sysref")
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phy = ttl_serdes_7series.Input_8X(sysref_pads.p, sysref_pads.n)
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phy = ttl_serdes_7series.Inout_8X(sysref_pads.p, sysref_pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
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ofifo_depth=2))
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phy = ttl_simple.Input(self.ad9154.jesd.jsync)
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phy = ttl_serdes_7series.Inout_8X(self.ad9154.jesd.jsync)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
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ofifo_depth=2))
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