mirror of https://github.com/m-labs/artiq.git
gateware: clean up and integrate QC2 modifications from Daniel
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fa1afb7dd8
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@ -18,6 +18,19 @@ fmc_adapter_io = [
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("ttl", 13, Pins("LPC:LA09_N"), IOStandard("LVTTL")),
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("ttl", 14, Pins("LPC:LA13_P"), IOStandard("LVTTL")),
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("ttl", 15, Pins("LPC:LA14_P"), IOStandard("LVTTL")),
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("ttl", 16, Pins("LPC:LA13_N"), IOStandard("LVTTL")),
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("ttl", 17, Pins("LPC:LA14_N"), IOStandard("LVTTL")),
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("ttl", 18, Pins("LPC:LA17_CC_P"), IOStandard("LVTTL")),
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("ttl", 19, Pins("LPC:LA17_CC_N"), IOStandard("LVTTL")),
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("ttl", 20, Pins("LPC:LA18_CC_P"), IOStandard("LVTTL")),
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("ttl", 21, Pins("LPC:LA18_CC_N"), IOStandard("LVTTL")),
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("ttl", 22, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
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("ttl", 23, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
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("ttl", 24, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
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("ttl", 25, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
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("ttl", 26, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
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("ttl", 27, Pins("LPC:LA26_N"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("LPC:LA22_N LPC:LA21_P LPC:LA22_P LPC:LA19_N "
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@ -28,7 +41,7 @@ fmc_adapter_io = [
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"LPC:LA04_N LPC:LA03_N LPC:LA04_P LPC:LA03_P")),
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Subsignal("sel_n", Pins("LPC:LA24_N LPC:LA29_P LPC:LA28_P LPC:LA29_N "
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"LPC:LA28_N LPC:LA31_P LPC:LA30_P LPC:LA31_N "
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"LPC:LA30_N LPC:LA33_P LPC:LA33_N")),
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"LPC:LA30_N LPC:LA33_P LPC:LA33_N LPC:LA32_P")),
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Subsignal("fud", Pins("LPC:LA21_N")),
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Subsignal("wr_n", Pins("LPC:LA24_P")),
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Subsignal("rd_n", Pins("LPC:LA25_N")),
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@ -36,7 +49,7 @@ fmc_adapter_io = [
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IOStandard("LVTTL")),
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("i2c", 0,
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Subsignal("scl", Pins("LPC:IIC_SLC")),
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Subsignal("scl", Pins("LPC:IIC_SCL")),
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Subsignal("sda", Pins("LPC:IIC_SDA")),
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IOStandard("LVCMOS25")),
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@ -50,29 +63,4 @@ fmc_adapter_io = [
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Subsignal("n", Pins("LPC:CLK1_M2C_N")),
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IOStandard("LVDS")),
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("la32", 0,
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Subsignal("p", Pins("LPC:LA32_P")),
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Subsignal("n", Pins("LPC:LA32_N")),
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IOStandard("LVDS")),
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("spi", 0,
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Subsignal("clk", Pins("LPC:LA13_N")),
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Subsignal("ce", Pins("LPC:LA14_N")),
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Subsignal("mosi", Pins("LPC:LA17_CC_P")),
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Subsignal("miso", Pins("LPC:LA17_CC_N")),
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IOStandard("LVTTL")),
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("spi", 1,
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Subsignal("clk", Pins("LPC:LA18_CC_P")),
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Subsignal("ce", Pins("LPC:LA18_CC_N")),
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Subsignal("mosi", Pins("LPC:LA23_P")),
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Subsignal("miso", Pins("LPC:LA23_N")),
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IOStandard("LVTTL")),
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("spi", 2,
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Subsignal("clk", Pins("LPC:LA27_P")),
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Subsignal("ce", Pins("LPC:LA26_P")),
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Subsignal("mosi", Pins("LPC:LA27_N")),
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Subsignal("miso", Pins("LPC:LA26_N")),
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IOStandard("LVTTL")),
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]
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@ -213,6 +213,10 @@ class NIST_QC1(_NIST_QCx):
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class NIST_QC2(_NIST_QCx):
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"""
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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and 12 DDS channels. Current implementation for single backplane.
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"""
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_QCx.__init__(self, cpu_type, **kwargs)
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@ -220,18 +224,16 @@ class NIST_QC2(_NIST_QCx):
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platform.add_extension(nist_qc2.fmc_adapter_io)
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rtio_channels = []
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for i in range(16):
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if i == 14:
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# TTL14 is for the clock generator
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continue
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if i % 4 == 3:
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phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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else:
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phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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# TTL0-23 are In+Out capable
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for i in range(24):
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phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
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# TTL24-26 are output only
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for i in range(24, 27):
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phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.Inout(platform.request("user_sma_gpio_n"))
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self.submodules += phy
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@ -241,15 +243,16 @@ class NIST_QC2(_NIST_QCx):
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
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phy = ttl_simple.ClockGen(platform.request("ttl", 14))
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# TTL27 is for the clock generator
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phy = ttl_simple.ClockGen(platform.request("ttl", 27))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
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self.config["DDS_CHANNEL_COUNT"] = 11
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self.config["DDS_CHANNEL_COUNT"] = 12
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self.config["DDS_AD9914"] = True
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self.config["DDS_ONEHOT_SEL"] = True
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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phy = dds.AD9914(platform.request("dds"), 12, onehot=True)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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ofifo_depth=512,
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