gateware.spi: ack only in cycles

2016-02-29 17:29:37 +01:00 · 2016-02-29 17:29:37 +01:00 · dd570720ac
parent a0083f4501
commit dd570720ac
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/spi.py
+++ b/artiq/gateware/spi.py
@ -310,7 +310,7 @@ class SPIMaster(Module):
            spi.div_read.eq(config.div_read),
        ]
        self.sync += [
-            bus.ack.eq(~bus.we | ~pending | spi.done),
+            bus.ack.eq(bus.cyc & bus.stb & (~bus.we | ~pending | spi.done)),
            If(wb_we,
               Array([data_write, xfer.raw_bits(), config.raw_bits()
                      ])[bus.adr].eq(bus.dat_w)