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drtio: RT RX datapath, untested
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146
artiq/gateware/drtio/rt_packets.py
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146
artiq/gateware/drtio/rt_packets.py
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.record import *
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class PacketLayoutManager:
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def __init__(self, alignment):
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self.alignment = alignment
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self.layouts = dict()
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self.types = dict()
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def add_type(self, name, *fields, pad=True):
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self.types[name] = len(self.types)
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layout = [("ty", 8)] + list(fields)
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misalignment = layout_len(layout) % self.alignment
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if misalignment:
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layout.append(("packet_pad", self.alignment - misalignment))
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self.layouts[name] = layout
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def get_m2s_layouts(alignment):
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plm = PacketLayoutManager(alignment)
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plm.add_type("echo_request")
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plm.add_type("set_time", ("timestamp", 64))
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plm.add_type("write", ("timestamp", 64),
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("channel", 16),
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("address", 16),
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("data_len", 8),
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("short_data", 8))
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plm.add_type("fifo_level_request", ("channel", 16))
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return plm
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def get_s2m_layouts(alignment):
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plm = PacketLayoutManager(alignment)
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plm.add_type("echo_reply")
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plm.add_type("fifo_level_reply", ("level", 24))
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return plm
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class ReceiveDatapath(Module):
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def __init__(self, ws, plm):
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# inputs
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self.frame = Signal()
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self.data = Signal(ws)
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# control
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self.packet_buffer_load = Signal()
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# outputs
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self.frame_r = Signal()
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self.data_r = Signal()
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self.packet_type = Signal(8)
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self.packet_last = Signal()
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self.packet_as = dict()
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# # #
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# input pipeline stage - determine packet length based on type
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lastword_per_type = [layout_len(l)//ws - 1
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for l in plm.layouts.values()]
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packet_last_n = Signal(max=max(lastword_per_type)+1)
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self.sync += [
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self.frame_r.eq(self.frame),
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self.data_r.eq(self.data),
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If(self.frame & ~self.frame_r,
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self.packet_type.eq(self.data[:8]),
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packet_last_n.eq(Array(lastword_per_type)[self.data[:8]])
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)
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]
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# bufferize packet
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packet_buffer = Signal(max(layout_len(l)
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for l in plm.layouts.values()))
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w_in_packet = len(packet_buffer)//ws
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packet_buffer_count = Signal(max=w_in_packet+1)
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self.sync += \
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If(self.packet_buffer_load,
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Case(packet_buffer_count,
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{i: packet_buffer[i*ws:(i+1)*ws].eq(self.data_r)
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for i in range(w_in_packet)}),
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packet_buffer_count.eq(packet_buffer_count + 1)
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).Else(
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packet_buffer_count.eq(0)
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)
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self.comb += self.packet_last.eq(packet_buffer_count == packet_last_n)
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# cast packet
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for name, layout in plm.layouts.items():
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self.packet_as[name] = Record(layout)
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self.comb += self.packet_as[name].raw_bits().eq(packet_buffer)
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class RTPacketSatellite(Module):
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def __init__(self, nwords):
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ws = 8*nwords
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self.rx_rt_frame = Signal()
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self.rx_rt_data = Signal(ws)
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self.tx_rt_frame = Signal()
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self.tx_rt_data = Signal(ws)
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# # #
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rx_plm = get_m2s_layouts(ws)
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rx_dp = ReceiveDatapath(ws, rx_plm)
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self.submodules += rx_dp
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self.comb += [
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rx_dp.frame.eq(self.rx_rt_frame),
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rx_dp.data.eq(self.rx_rt_data)
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]
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fsm = FSM(reset_state="WAIT_FRAME")
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self.submodules += fsm
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continuation = Signal()
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continuation_r = Signal()
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frame_r_r = Signal()
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self.sync += [
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continuation_r.eq(continuation),
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frame_r_r.eq(rx_dp.frame_r)
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]
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fsm.act("WAIT_INPUT",
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If(rx_dp.frame_r,
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If(~frame_r_r | continuation_r,
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continuation.eq(1),
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packet_buffer_load.eq(1),
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If(rx_dp.packet_last,
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Case(rx_dp.packet_type, {
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rx_plm.types["echo_request"]: NextState("ECHO"),
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"default": NextState("ERROR_UNKNOWN_TYPE")
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})
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)
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).Else(
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NextState("ERROR_FRAME_MISSED")
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)
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)
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)
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fsm.state("ECHO",
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NextState("WAIT_INPUT")
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)
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fsm.state("ERROR_FRAME_MISSED",
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NextState("WAIT_INPUT")
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)
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fsm.state("ERROR_UNKNOWN_TYPE",
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NextState("WAIT_INPUT")
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)
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