sawg: add register after hbf for timing

2024-12-25 03:08:27 +08:00 · 2017-06-12 23:08:27 +02:00 · 2017-06-12 23:08:27 +02:00 · e229edd5d5
commit e229edd5d5
parent 315338fca9
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/dsp/sawg.py
+++ b/artiq/gateware/dsp/sawg.py
@ -172,7 +172,7 @@ class Channel(Module, SatAddMixin):
            Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr),
        ]
        for i in range(parallelism):
-            self.comb += [
+            self.sync += [
                b.xi[i].eq(self.sat_add(hbf[0].o[i],
                                     limits=cfg.limits[0],
                                     clipped=cfg.clipped[0])),