artiq/artiq/gateware
Sebastien Bourdeauducq 8cfe2ec53a rtio/sed: fix sequence number width computation 2017-09-13 22:11:41 +08:00
..
amp gateware: use new MiSoC Wishbone address system 2017-07-13 19:16:49 +08:00
drtio drtio: multilink transceiver interface 2017-07-18 13:27:33 +08:00
dsp Revert "sawg: advance dds 1/2 by one sample group" 2017-07-04 17:55:19 +02:00
rtio rtio/sed: fix sequence number width computation 2017-09-13 22:11:41 +08:00
targets kc705_sma_spi: fix permissions 2017-08-20 10:54:24 -04:00
test rtio/sed: add lane distributor simulation unittest 2017-09-13 18:00:16 +08:00
__init__.py artiqlib -> artiq.gateware 2015-03-08 11:00:24 +01:00
ad9_dds.py ad9xxx -> ad9_dds 2017-01-04 11:34:52 +01:00
ad9154_fmc_ebz.py Merge remote-tracking branch 'm-labs/phaser2' into phaser2 2016-12-02 14:11:56 +01:00
nist_clock.py gateware/nist_clock: increase DDS bus drive strength. Closes #468 2016-06-07 11:08:19 -04:00
nist_qc2.py qc2: swap SPI/TTL, all TTL lines are now In+Out compatible 2016-05-19 10:42:03 +08:00
spi.py spi: fix xfers with full data_width (closes #615) 2017-01-03 19:51:14 +01:00