mirror of https://github.com/m-labs/artiq.git
sawg: register pre-hbf adder
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@ -150,7 +150,7 @@ class Channel(Module, SatAddMixin):
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self.u.latency += 1
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b.p.latency += 2
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b.f.latency += 2
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a_latency_delta = hbf[0].latency + b.latency + 2
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a_latency_delta = hbf[0].latency + b.latency + 3
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for a in a1, a2:
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a.a.latency += a_latency_delta
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a.p.latency += a_latency_delta
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@ -185,7 +185,7 @@ class Channel(Module, SatAddMixin):
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# correct pre-DUC limiter by cordic gain
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v = cfg.limits[i][j].reset.value
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cfg.limits[i][j].reset.value = int(v / b.gain)
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self.comb += [
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self.sync += [
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hbf[0].i.eq(a1.xo[0] + a2.xo[0]),
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hbf[1].i.eq(a1.yo[0] + a2.yo[0])
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]
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