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add information about CLOCK hardware
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artiq/gateware/nist_clock.py
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76
artiq/gateware/nist_clock.py
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@ -0,0 +1,76 @@
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from migen.build.generic_platform import *
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fmc_adapter_io = [
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("ttl", 0, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
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("ttl", 1, Pins("LPC:LA02_P"), IOStandard("LVTTL")),
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("ttl", 2, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
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("ttl", 3, Pins("LPC:LA02_N"), IOStandard("LVTTL")),
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("ttl", 4, Pins("LPC:LA01_CC_N"), IOStandard("LVTTL")),
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("ttl", 5, Pins("LPC:LA06_P"), IOStandard("LVTTL")),
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("ttl", 6, Pins("LPC:LA06_N"), IOStandard("LVTTL")),
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("ttl", 7, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
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("ttl", 8, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
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("ttl", 9, Pins("LPC:LA05_N"), IOStandard("LVTTL")),
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("ttl", 10, Pins("LPC:LA05_P"), IOStandard("LVTTL")),
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("ttl", 11, Pins("LPC:LA09_P"), IOStandard("LVTTL")),
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("ttl", 12, Pins("LPC:LA09_N"), IOStandard("LVTTL")),
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("ttl", 13, Pins("LPC:LA13_P"), IOStandard("LVTTL")),
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("ttl", 14, Pins("LPC:LA14_P"), IOStandard("LVTTL")),
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("ttl", 15, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
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("pmt", 0, Pins("LPC:CLK0_M2C_P"), IOStandard("LVTTL")),
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("pmt", 1, Pins("LPC:CLK0_M2C_N"), IOStandard("LVTTL")),
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("dds", 0,
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Subsignal("a", Pins("LPC:LA22_N LPC:LA21_P LPC:LA22_P LPC:LA19_N "
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"LPC:LA20_N LPC:LA19_P LPC:LA20_P")),
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Subsignal("d", Pins("LPC:LA15_N LPC:LA16_N LPC:LA15_P LPC:LA16_P "
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"LPC:LA11_N LPC:LA12_N LPC:LA11_P LPC:LA12_P "
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"LPC:LA07_N LPC:LA08_N LPC:LA07_P LPC:LA08_P "
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"LPC:LA04_N LPC:LA03_N LPC:LA04_P LPC:LA03_P")),
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Subsignal("sel_n", Pins("LPC:LA24_N LPC:LA29_P LPC:LA28_P LPC:LA29_N "
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"LPC:LA28_N LPC:LA31_P LPC:LA30_P LPC:LA31_N "
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"LPC:LA30_N LPC:LA33_P LPC:LA33_N")),
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Subsignal("fud", Pins("LPC:LA21_N")),
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Subsignal("wr_n", Pins("LPC:LA24_P")),
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Subsignal("rd_n", Pins("LPC:LA25_N")),
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Subsignal("rst", Pins("LPC:LA25_P")),
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IOStandard("LVTTL")),
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("i2c", 0,
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Subsignal("scl", Pins("LPC:IIC_SLC")),
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Subsignal("sda", Pins("LPC:IIC_SDA")),
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IOStandard("LVCMOS25")),
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("clk_m2c", 1,
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Subsignal("p", Pins("LPC:CLK1_M2C_P")),
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Subsignal("n", Pins("LPC:CLK1_M2C_N")),
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IOStandard("LVDS")),
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("la32", 0,
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Subsignal("p", Pins("LPC:LA32_P")),
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Subsignal("n", Pins("LPC:LA32_N")),
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IOStandard("LVDS")),
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("spi", 0,
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Subsignal("clk", Pins("LPC:LA13_N")),
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Subsignal("ce", Pins("LPC:LA14_N")),
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Subsignal("mosi", Pins("LPC:LA17_CC_P")),
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Subsignal("miso", Pins("LPC:LA17_CC_N")),
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IOStandard("LVTTL")),
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("spi", 1,
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Subsignal("clk", Pins("LPC:LA23_N")),
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Subsignal("ce", Pins("LPC:LA23_P")),
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Subsignal("mosi", Pins("LPC:LA18_CC_N")),
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Subsignal("miso", Pins("LPC:LA18_CC_P")),
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IOStandard("LVTTL")),
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("spi", 2,
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Subsignal("clk", Pins("LPC:LA27_P")),
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Subsignal("ce", Pins("LPC:LA26_P")),
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Subsignal("mosi", Pins("LPC:LA27_N")),
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Subsignal("miso", Pins("LPC:LA26_N")),
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IOStandard("LVTTL")),
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]
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@ -27,7 +27,7 @@ FPGA board ports
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KC705
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-----
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The main target board for the ARTIQ core device is the KC705 development board from Xilinx. It supports the NIST QC1 hardware via an adapter, and the NIST QC2 hardware (FMC).
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The main target board for the ARTIQ core device is the KC705 development board from Xilinx. It supports the NIST QC1 hardware via an adapter, and the NIST CLOCK and QC2 hardware (FMC).
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With the QC1 hardware, the TTL lines are mapped as follows:
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@ -47,6 +47,25 @@ With the QC1 hardware, the TTL lines are mapped as follows:
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| 19 | TTL15 | Clock |
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+--------------+------------+--------------+
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With the CLOCK hardware, the TTL lines are mapped as follows:
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+--------------------+-----------------------+--------------+
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| RTIO channel | TTL line | Capability |
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+====================+=======================+==============+
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| 3,7,11,15 | TTL3,7,11,15 | Input+Output |
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+--------------------+-----------------------+--------------+
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| 0-2,4-6,8-10,12-14 | TTL0-2,4-6,8-10,12-14 | Output |
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+--------------------+-----------------------+--------------+
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| 16 | PMT0 | Input |
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+--------------------+-----------------------+--------------+
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| 17 | PMT1 | Input |
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+--------------------+-----------------------+--------------+
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| 18 | SMA_GPIO_N | Input+Output |
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+--------------------+-----------------------+--------------+
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| 19 | LED | Output |
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+--------------------+-----------------------+--------------+
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Pipistrello
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-----------
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