mirror of https://github.com/m-labs/artiq.git
drtio: collision/replace fixes
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83d87b5805
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@ -50,6 +50,9 @@ class IOS(Module):
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we = Signal()
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self.comb += we.eq(rt_packet.write_stb
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& (rt_packet.write_channel == n))
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write_timestamp = rt_packet.write_timestamp[max_fine_ts_width-fine_ts_width:]
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write_timestamp_coarse = rt_packet.write_timestamp[max_fine_ts_width:]
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write_timestamp_fine = rt_packet.write_timestamp[max_fine_ts_width-fine_ts_width:max_fine_ts_width]
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# latency compensation
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if interface.delay:
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@ -89,11 +92,10 @@ class IOS(Module):
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if interface.enable_replace:
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# Note: replace may be asserted at the same time as collision
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# when addresses are different. In that case, it is a collision.
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self.sync.rio += replace.eq(rt_packet.write_timestamp == buf.timestamp)
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# Detect sequence errors on coarse timestamps only
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# so that they are mutually exclusive with collision errors.
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self.sync.rio += sequence_error.eq(rt_packet.write_timestamp[fine_ts_width:] <
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buf.timestamp[fine_ts_width:])
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self.sync.rio += replace.eq(write_timestamp == buf.timestamp)
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# Detect sequence errors on coarse timestamps only
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# so that they are mutually exclusive with collision errors.
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self.sync.rio += sequence_error.eq(write_timestamp_coarse < buf.timestamp[fine_ts_width:])
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if interface.enable_replace:
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if address_width:
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different_addresses = rt_packet.write_address != buf.address
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@ -101,12 +103,15 @@ class IOS(Module):
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different_addresses = 0
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if fine_ts_width:
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self.sync.rio += collision.eq(
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(rt_packet.write_timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
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& ((rt_packet.write_timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])
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(write_timestamp_coarse == buf.timestamp[fine_ts_width:])
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& ((write_timestamp_fine != buf.timestamp[:fine_ts_width])
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|different_addresses))
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else:
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self.sync.rio += collision.eq(
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(write_timestamp == buf.timestamp) & different_addresses)
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else:
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self.sync.rio += collision.eq(
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rt_packet.write_timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:])
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write_timestamp_coarse == buf.timestamp[fine_ts_width:])
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self.comb += any_error.eq(sequence_error | collision)
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self.sync.rio += [
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If(we & sequence_error, self.write_sequence_error.eq(1)),
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@ -142,8 +147,7 @@ class IOS(Module):
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If(we & ~any_error,
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buf_just_written.eq(1),
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buf_pending.eq(1),
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buf.timestamp.eq(
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rt_packet.write_timestamp[max_fine_ts_width-fine_ts_width:]),
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buf.timestamp.eq(write_timestamp),
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buf.data.eq(rt_packet.write_data) if data_width else [],
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buf.address.eq(rt_packet.write_address) if address_width else [],
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),
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