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gateware/serwb: generate wishbone error on wishbone slave when access while link is not ready

This commit is contained in:
Florent Kermarrec 2017-08-29 13:43:26 +02:00
parent 89558e2653
commit 60ad36e7d6
2 changed files with 13 additions and 4 deletions
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16
artiq/gateware/serwb/etherbone.py
View File

@ -645,6 +645,7 @@ class EtherboneWishboneMaster(Module):
class EtherboneWishboneSlave(Module):
def __init__(self):
self.bus = bus = wishbone.Interface()
self.ready = Signal(reset=1)
self.sink = sink = stream.Endpoint(etherbone_mmap_description(32))
self.source = source = stream.Endpoint(etherbone_mmap_description(32))
@ -654,10 +655,14 @@ class EtherboneWishboneSlave(Module):
fsm.act("IDLE",
sink.ack.eq(1),
If(bus.stb & bus.cyc,
If(bus.we,
NextState("SEND_WRITE")
If(self.ready,
If(bus.we,
NextState("SEND_WRITE")
).Else(
NextState("SEND_READ")
)
).Else(
NextState("SEND_READ")
NextState("SEND_ERROR")
)
)
)
@ -694,7 +699,10 @@ class EtherboneWishboneSlave(Module):
NextState("IDLE")
)
)
fsm.act("SEND_ERROR",
bus.ack.eq(1),
bus.err.eq(1)
)
# etherbone

1
artiq/gateware/targets/sayma_amc_standalone.py
View File

@ -86,6 +86,7 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
self.submodules += serwb_depacketizer, serwb_packetizer
serwb_etherbone = serwb.etherbone.Etherbone(mode="slave")
self.submodules += serwb_etherbone
self.comb += serwb_etherbone.wishbone.ready.eq(serwb_init.ready)
serwb_tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serdes"})(
stream.AsyncFIFO([("data", 32)], 8))
self.submodules += serwb_tx_cdc