mirror of https://github.com/m-labs/artiq.git
drtio: more reliable link layer init
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c92ccd3b5b
commit
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@ -6,9 +6,10 @@ from artiq.gateware.drtio import link_layer, rt_packets, iot, rt_controller
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class DRTIOSatellite(Module):
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def __init__(self, transceiver, rx_synchronizer, channels, fine_ts_width=3, full_ts_width=63):
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def __init__(self, transceiver, rx_synchronizer, channels, fine_ts_width=3, full_ts_width=63,
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ll_rx_ready_confirm=1000):
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self.submodules.link_layer = link_layer.LinkLayer(
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transceiver.encoder, transceiver.decoders)
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transceiver.encoder, transceiver.decoders, ll_rx_ready_confirm)
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self.comb += [
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transceiver.rx_reset.eq(self.link_layer.rx_reset),
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self.link_layer.rx_ready.eq(transceiver.rx_ready)
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@ -45,9 +46,9 @@ class DRTIOSatellite(Module):
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class DRTIOMaster(Module):
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def __init__(self, transceiver, channel_count=1024, fine_ts_width=3):
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def __init__(self, transceiver, channel_count=1024, fine_ts_width=3, ll_rx_ready_confirm=1000):
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self.submodules.link_layer = link_layer.LinkLayer(
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transceiver.encoder, transceiver.decoders)
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transceiver.encoder, transceiver.decoders, ll_rx_ready_confirm)
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self.comb += [
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transceiver.rx_reset.eq(self.link_layer.rx_reset),
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self.link_layer.rx_ready.eq(transceiver.rx_ready)
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@ -4,6 +4,7 @@ from operator import xor, or_
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.cdc import MultiReg, BusSynchronizer
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from migen.genlib.misc import WaitTimer
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from misoc.interconnect.csr import *
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@ -212,7 +213,7 @@ class LinkLayerRX(Module):
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class LinkLayer(Module, AutoCSR):
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def __init__(self, encoder, decoders):
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def __init__(self, encoder, decoders, rx_ready_confirm_cycles):
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self.link_status = CSRStatus(3)
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# control signals, in rtio clock domain
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@ -272,6 +273,12 @@ class LinkLayer(Module, AutoCSR):
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self.submodules += link_status
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self.comb += self.link_status.status.eq(link_status.o)
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wait_confirm = ClockDomainsRenamer("rtio")(
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WaitTimer(rx_ready_confirm_cycles))
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self.submodules += wait_confirm
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signal_rx_ready_margin = ClockDomainsRenamer("rtio")(WaitTimer(15))
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self.submodules += signal_rx_ready_margin
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fsm.act("RESET_RX",
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link_status.i.eq(0),
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tx.link_init.eq(1),
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@ -281,24 +288,40 @@ class LinkLayer(Module, AutoCSR):
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fsm.act("WAIT_LOCAL_RX_READY",
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link_status.i.eq(1),
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tx.link_init.eq(1),
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If(self.rx_ready,
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NextState("WAIT_REMOTE_RX_READY")
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)
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If(self.rx_ready, NextState("CONFIRM_LOCAL_RX_READY"))
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)
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fsm.act("WAIT_REMOTE_RX_READY",
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fsm.act("CONFIRM_LOCAL_RX_READY",
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link_status.i.eq(2),
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tx.link_init.eq(1),
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wait_confirm.wait.eq(1),
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If(wait_confirm.done, NextState("WAIT_REMOTE_RX_READY")),
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If(~rx_link_init, NextState("RESET_RX"))
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)
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fsm.act("WAIT_REMOTE_RX_READY",
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link_status.i.eq(3),
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tx.link_init.eq(1),
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tx.signal_rx_ready.eq(1),
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If(rx_remote_rx_ready,
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NextState("WAIT_REMOTE_LINK_UP")
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)
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If(rx_remote_rx_ready, NextState("ENSURE_SIGNAL_RX_READY"))
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)
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# If the transceiver transmits one character per RTIO cycle,
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# we may be unlucky and signal_rx_ready will transmit a comma
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# on the first cycle instead of a "RX ready" character.
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# Further, we need to ensure the rx.remote_rx_ready
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# gets through MultiReg to rx_remote_rx_ready at the receiver.
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# So transmit the "RX ready" pattern for several cycles.
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fsm.act("ENSURE_SIGNAL_RX_READY",
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link_status.i.eq(3),
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tx.link_init.eq(1),
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tx.signal_rx_ready.eq(1),
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signal_rx_ready_margin.wait.eq(1),
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If(signal_rx_ready_margin.done, NextState("WAIT_REMOTE_LINK_UP"))
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)
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fsm.act("WAIT_REMOTE_LINK_UP",
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link_status.i.eq(3),
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link_status.i.eq(4),
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If(~rx_link_init, NextState("READY"))
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)
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fsm.act("READY",
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link_status.i.eq(4),
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If(rx_link_init, NextState("RESET_RX")),
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link_status.i.eq(5),
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If(rx_link_init, NextState("RESET_RX")), # TODO: remove this, link deinit should be detected at upper layer
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self.ready.eq(1)
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)
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@ -3,7 +3,7 @@ use sched::{Waiter, Spawner};
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fn drtio_link_is_up() -> bool {
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unsafe {
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csr::drtio::link_status_read() == 4
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csr::drtio::link_status_read() == 5
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}
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}
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@ -41,7 +41,8 @@ class DUT(Module):
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self.ttl1 = Signal()
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self.transceivers = DummyTransceiverPair(nwords)
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self.submodules.master = DRTIOMaster(self.transceivers.alice)
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self.submodules.master = DRTIOMaster(self.transceivers.alice,
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ll_rx_ready_confirm=15)
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rx_synchronizer = DummyRXSynchronizer()
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self.submodules.phy0 = ttl_simple.Output(self.ttl0)
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@ -51,7 +52,8 @@ class DUT(Module):
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rtio.Channel.from_phy(self.phy1, ofifo_depth=4)
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]
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self.submodules.satellite = DRTIOSatellite(
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self.transceivers.bob, rx_synchronizer, rtio_channels)
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self.transceivers.bob, rx_synchronizer, rtio_channels,
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ll_rx_ready_confirm=15)
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class TestFullStack(unittest.TestCase):
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