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gateware/rtio/analyzer: fix bus write

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This commit is contained in:
Sebastien Bourdeauducq 2015-12-18 15:44:20 +08:00
parent f431add20e
commit 59a3ea4f15
1 changed files with 5 additions and 3 deletions
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8
artiq/gateware/rtio/analyzer.py
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@ -187,11 +187,8 @@ class DMAWriter(Module, AutoCSR):
)
fsm.act("WRITE",
self.busy.status.eq(1),
membus.cyc.eq(1),
membus.stb.eq(1),
membus.we.eq(1),
membus.sel.eq(2**len(membus.sel)-1),
If(membus.ack,
If(membus.adr == self.last_address.storage,
@ -204,6 +201,11 @@ class DMAWriter(Module, AutoCSR):
NextState("IDLE")
)
)
self.comb += [
membus.we.eq(1),
membus.sel.eq(2**len(membus.sel)-1),
membus.dat_w.eq(self.sink.data)
]
class Analyzer(Module, AutoCSR):