mirror of https://github.com/m-labs/artiq.git
targets/kc705: enable I2C for all hardware adapters
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@ -94,8 +94,11 @@ _ams101_dac = [
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class _NIST_Ions(MiniSoC, AMPSoC):
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csr_map = {
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"timer_kernel": None, # mapped on Wishbone instead
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"rtio": None, # mapped on Wishbone instead
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# mapped on Wishbone instead
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"timer_kernel": None,
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"rtio": None,
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"i2c": None,
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"rtio_crg": 13,
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"kernel_cpu": 14,
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"rtio_moninj": 15,
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@ -105,6 +108,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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mem_map = {
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"timer_kernel": 0x10000000, # (shadow @0x90000000)
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"rtio": 0x20000000, # (shadow @0xa0000000)
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"i2c": 0x30000000, # (shadow @0xb0000000)
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(MiniSoC.mem_map)
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@ -131,6 +135,11 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.platform.add_extension(_ams101_dac)
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.register_kernel_cpu_csrdevice("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.submodules.rtio = rtio.RTIO(rtio_channels)
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@ -293,15 +302,6 @@ class NIST_QC2(_NIST_Ions):
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NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
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and 12 DDS channels. Current implementation for single backplane.
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"""
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csr_map = {
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"i2c": None
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}
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csr_map.update(_NIST_Ions.csr_map)
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mem_map = {
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"i2c": 0x30000000 # (shadow @0xb0000000)
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}
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mem_map.update(_NIST_Ions.mem_map)
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def __init__(self, cpu_type="or1k", **kwargs):
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_NIST_Ions.__init__(self, cpu_type, **kwargs)
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@ -350,11 +350,6 @@ class NIST_QC2(_NIST_Ions):
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assert self.rtio.fine_ts_width <= 3
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self.config["DDS_RTIO_CLK_RATIO"] = 24 >> self.rtio.fine_ts_width
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i2c = platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.register_kernel_cpu_csrdevice("i2c")
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self.config["I2C_BUS_COUNT"] = 1
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def main():
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parser = argparse.ArgumentParser(
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