mirror of https://github.com/m-labs/artiq.git
sma_spi: undo cri_con
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@ -127,7 +127,6 @@ class SMA_SPI(_NIST_Ions):
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri])
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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self.csr_devices.append("rtio_moninj")
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