mirror of https://github.com/m-labs/artiq.git
drtio: reset more local state
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d99e64effd
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4b61020b27
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@ -1,6 +1,7 @@
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.misc import WaitTimer
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.interconnect.csr import *
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@ -70,6 +71,18 @@ class RTController(Module):
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),
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]
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local_reset = Signal(reset=1)
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self.sync += local_reset.eq(self.csrs.reset.re)
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local_reset.attr.add("no_retiming")
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self.clock_domains.cd_rsys = ClockDomain()
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self.clock_domains.cd_rio = ClockDomain()
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self.comb += [
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self.cd_rsys.clk.eq(ClockSignal()),
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self.cd_rsys.rst.eq(local_reset)
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]
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self.comb += self.cd_rio.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(self.cd_rio, local_reset)
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# remote channel status cache
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fifo_spaces_mem = Memory(16, channel_count)
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fifo_spaces = fifo_spaces_mem.get_port(write_capable=True)
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@ -94,7 +107,7 @@ class RTController(Module):
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)
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]
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fsm = FSM()
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fsm = ClockDomainsRenamer("rsys")(FSM())
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self.submodules += fsm
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status_wait = Signal()
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@ -107,15 +120,11 @@ class RTController(Module):
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]
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sequence_error_set = Signal()
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underflow_set = Signal()
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self.sync += [
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self.sync.rio += [
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If(self.cri.cmd == cri.commands["o_underflow_reset"], status_underflow.eq(0)),
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If(self.cri.cmd == cri.commands["o_sequence_error_reset"], status_sequence_error.eq(0)),
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If(underflow_set, status_underflow.eq(1)),
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If(sequence_error_set, status_sequence_error.eq(1)),
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If(self.csrs.reset.re,
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status_underflow.eq(0),
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status_sequence_error.eq(0)
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)
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If(sequence_error_set, status_sequence_error.eq(1))
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]
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signal_fifo_space_timeout = Signal()
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@ -487,7 +487,7 @@ class RTPacketMaster(Module):
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self.submodules += rx_dp
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# Write FIFO and extra data count
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wfifo = ClockDomainsRenamer({"write": "sys", "read": "rtio"})(
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wfifo = ClockDomainsRenamer({"write": "rsys", "read": "rio"})(
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AsyncFIFO(64+16+16+512, write_fifo_depth))
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self.submodules += wfifo
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write_timestamp_d = Signal(64)
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@ -66,7 +66,8 @@ class DUT(Module):
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class TestFullStack(unittest.TestCase):
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clocks = {"sys": 8, "rtio": 5, "rtio_rx": 5, "rio": 5, "rio_phy": 5}
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clocks = {"sys": 8, "rtio": 5, "rtio_rx": 5,
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"rsys": 8, "rio": 5, "rio_phy": 5}
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def test_controller(self):
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dut = DUT(2)
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