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artiq
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targets: kc705 -> kc705_dds

This commit is contained in:
Sebastien Bourdeauducq 2017-01-05 18:40:56 +01:00
parent 8be9a827ba
commit fe53bab953
9 changed files with 10 additions and 11 deletions
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2
artiq/frontend/artiq_devtool.py
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@ -84,7 +84,7 @@ def main():
if action == "build":
logger.info("Building runtime")
try:
subprocess.check_call(["python3", "-m", "artiq.gateware.targets.kc705",
subprocess.check_call(["python3", "-m", "artiq.gateware.targets.kc705_dds",
"-H", "nist_clock",
"--no-compile-gateware",
"--output-dir", "/tmp/kc705"])

4
artiq/gateware/targets/kc705.py → artiq/gateware/targets/kc705_dds.py
View File

@ -314,8 +314,8 @@ class NIST_QC2(_NIST_Ions):
def main():
parser = argparse.ArgumentParser(
description="ARTIQ core device builder / KC705 "
"+ NIST Ions CLOCK/QC2 hardware adapters")
description="ARTIQ device binary builder / single-FPGA KC705-based "
"systems with AD9 DDS (NIST Ions hardware)")
builder_args(parser)
soc_kc705_args(parser)
parser.add_argument("-H", "--hw-adapter", default="nist_clock",

2
artiq/gateware/targets/kc705_drtio_master.py
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@ -105,7 +105,7 @@ class Master(MiniSoC, AMPSoC):
def main():
parser = argparse.ArgumentParser(
description="ARTIQ with DRTIO on KC705 - Master")
description="ARTIQ device binary builder / KC705 DRTIO master")
builder_args(parser)
soc_kc705_args(parser)
parser.add_argument("-c", "--config", default="simple_gbe",

2
artiq/gateware/targets/kc705_drtio_satellite.py
View File

@ -202,7 +202,7 @@ class Satellite(BaseSoC):
def main():
parser = argparse.ArgumentParser(
description="ARTIQ with DRTIO on KC705 - Satellite")
description="ARTIQ device binary builder / KC705 DRTIO satellite")
builder_args(parser)
soc_kc705_args(parser)
parser.add_argument("-c", "--config", default="simple_gbe",

3
artiq/gateware/targets/phaser.py
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@ -257,8 +257,7 @@ class Phaser(MiniSoC, AMPSoC):
def main():
parser = argparse.ArgumentParser(
description="ARTIQ core device builder for "
"KC705+AD9154 hardware")
description="ARTIQ device binary builder / KC705 phaser demo")
builder_args(parser)
soc_kc705_args(parser)
args = parser.parse_args()

2
artiq/gateware/targets/pipistrello.py
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@ -229,7 +229,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
def main():
parser = argparse.ArgumentParser(
description="ARTIQ core device builder / Pipistrello demo")
description="ARTIQ device binary builder / Pipistrello demo")
builder_args(parser)
soc_pipistrello_args(parser)
args = parser.parse_args()

2
conda/artiq-kc705-nist_clock/build.sh
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@ -6,7 +6,7 @@ BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-nist_clock
mkdir -p $SOC_PREFIX
$PYTHON -m artiq.gateware.targets.kc705 -H nist_clock --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
$PYTHON -m artiq.gateware.targets.kc705_dds -H nist_clock --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
cp misoc_nist_clock_kc705/gateware/top.bit $SOC_PREFIX
cp misoc_nist_clock_kc705/software/bios/bios.bin $SOC_PREFIX
cp misoc_nist_clock_kc705/software/runtime/runtime.fbi $SOC_PREFIX

2
conda/artiq-kc705-nist_qc2/build.sh
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@ -6,7 +6,7 @@ BUILD_SETTINGS_FILE=$HOME/.m-labs/build_settings.sh
SOC_PREFIX=$PREFIX/lib/python3.5/site-packages/artiq/binaries/kc705-nist_qc2
mkdir -p $SOC_PREFIX
$PYTHON -m artiq.gateware.targets.kc705 -H nist_qc2 --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
$PYTHON -m artiq.gateware.targets.kc705_dds -H nist_qc2 --toolchain vivado $MISOC_EXTRA_VIVADO_CMDLINE
cp misoc_nist_qc2_kc705/gateware/top.bit $SOC_PREFIX
cp misoc_nist_qc2_kc705/software/bios/bios.bin $SOC_PREFIX
cp misoc_nist_qc2_kc705/software/runtime/runtime.fbi $SOC_PREFIX

2
doc/manual/installing_from_source.rst
View File

@ -170,7 +170,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
* For KC705::
$ python3.5 -m artiq.gateware.targets.kc705 -H nist_clock # or nist_qc2
$ python3.5 -m artiq.gateware.targets.kc705_dds -H nist_clock # or nist_qc2
.. note:: Add ``--toolchain ise`` if you wish to use ISE instead of Vivado.