soc: rtio monitor

artiq/gateware/rtio/__init__.py

@@ -1 +1,2 @@
 from artiq.gateware.rtio.core import Channel, RTIO
+from artiq.gateware.rtio.monitor import Monitor

artiq/gateware/rtio/core.py

@@ -247,8 +247,9 @@ class _InputManager(Module):
 
 
 class Channel:
-    def __init__(self, interface, ofifo_depth=64, ififo_depth=64):
+    def __init__(self, interface, probes=[], ofifo_depth=64, ififo_depth=64):
         self.interface = interface
+        self.probes = probes
         self.ofifo_depth = ofifo_depth
         self.ififo_depth = ififo_depth
 

artiq/gateware/rtio/monitor.py

@@ -0,0 +1,28 @@
+from migen.fhdl.std import *
+from migen.bank.description import *
+from migen.genlib.cdc import BusSynchronizer
+
+class Monitor(Module, AutoCSR):
+    def __init__(self, channels):
+        chan_probes = [c.probes for c in channels]
+
+        max_chan_probes = max(len(cp) for cp in chan_probes)
+        max_probe_len = max(flen(p) for cp in chan_probes for p in cp)
+        self.chan_sel = CSRStorage(bits_for(len(chan_probes)-1))
+        self.probe_sel = CSRStorage(bits_for(max_chan_probes-1))
+        self.probe_value = CSRStatus(max_probe_len)
+
+        # # #
+
+        chan_probes_sys = []
+        for cp in chan_probes:
+            cp_sys = []
+            for p in cp:
+                vs = BusSynchronizer(flen(p), "rio", "rsys")
+                self.submodules += vs
+                self.comb += vs.i.eq(p)
+                cp_sys.append(vs.o)
+            cp_sys += [0]*(max_chan_probes-len(cp))
+            chan_probes_sys.append(Array(cp_sys)[self.probe_sel.storage])
+        self.comb += self.probe_value.status.eq(
+            Array(chan_probes_sys)[self.chan_sel.storage])

artiq/gateware/rtio/phy/ttl_simple.py

@@ -7,6 +7,7 @@ from artiq.gateware.rtio import rtlink
 class Output(Module):
     def __init__(self, pad):
         self.rtlink = rtlink.Interface(rtlink.OInterface(1))
+        self.probes = [pad]
 
         # # #
 
@@ -18,6 +19,7 @@ class Inout(Module):
         self.rtlink = rtlink.Interface(
             rtlink.OInterface(2, 2),
             rtlink.IInterface(1))
+        self.probes = []
 
         # # #
         
@@ -43,3 +45,5 @@ class Inout(Module):
             ),
             self.rtlink.i.data.eq(i)
         ]
+
+        self.probes += [i, ts.oe]

soc/runtime/session.c

@@ -154,7 +154,7 @@ static int process_input(void)
                 submit_output(9);
                 break;    
             }
-            rtiocrg_clock_sel_write(buffer_in[9]);
+            rtio_crg_clock_sel_write(buffer_in[9]);
             buffer_out[8] = REMOTEMSG_TYPE_CLOCK_SWITCH_COMPLETED;
             submit_output(9);
             break;

soc/runtime/test_mode.c

@@ -47,7 +47,7 @@ static void clksrc(char *value)
         return;
     }
 
-    rtiocrg_clock_sel_write(value2);
+    rtio_crg_clock_sel_write(value2);
 }
 
 static void ttloe(char *n, char *value)

soc/targets/artiq_kc705.py

@@ -35,8 +35,9 @@ class _RTIOCRG(Module, AutoCSR):
 class NIST_QC1(MiniSoC, AMPSoC):
     csr_map = {
         "rtio": None,  # mapped on Wishbone instead
-        "rtiocrg": 13,
-        "kernel_cpu": 14
+        "rtio_crg": 13,
+        "kernel_cpu": 14,
+        "rtio_mon": 15
     }
     csr_map.update(MiniSoC.csr_map)
     mem_map = {
@@ -65,15 +66,16 @@ class NIST_QC1(MiniSoC, AMPSoC):
         for i in range(2):
             phy = ttl_simple.Inout(platform.request("pmt", i))
             self.submodules += phy
-            rtio_channels.append(rtio.Channel(phy.rtlink, ififo_depth=512))
+            rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes,
+                                              ififo_depth=512))
         for i in range(16):
             phy = ttl_simple.Output(platform.request("ttl", i))
             self.submodules += phy
-            rtio_channels.append(rtio.Channel(phy.rtlink))
+            rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
 
         phy = ttl_simple.Output(platform.request("user_led", 2))
         self.submodules += phy
-        rtio_channels.append(rtio.Channel(phy.rtlink))
+        rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
 
         self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
         self.submodules.dds = RenameClockDomains(
@@ -84,11 +86,11 @@ class NIST_QC1(MiniSoC, AMPSoC):
         rtio_channels.append(rtio.Channel(phy.rtlink, ififo_depth=4))
 
         # RTIO core
-        self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)
+        self.submodules.rtio_crg = _RTIOCRG(platform, self.crg.pll_sys)
         self.submodules.rtio = rtio.RTIO(rtio_channels,
                                          clk_freq=125000000)
         self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
-
+        self.submodules.rtio_mon = rtio.Monitor(rtio_channels)
 
         if isinstance(platform.toolchain, XilinxVivadoToolchain):
             platform.add_platform_command("""

soc/targets/artiq_pipistrello.py

@@ -56,8 +56,9 @@ TIMESPEC "TSfix_ise6" = FROM "GRPint_clk" TO "GRPext_clk" TIG;
 class NIST_QC1(BaseSoC, AMPSoC):
     csr_map = {
         "rtio": None,  # mapped on Wishbone instead
-        "rtiocrg": 13,
-        "kernel_cpu": 14
+        "rtio_crg": 13,
+        "kernel_cpu": 14,
+        "rtio_mon": 15
     }
     csr_map.update(BaseSoC.csr_map)
     mem_map = {
@@ -90,25 +91,26 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         for i in range(2):
             phy = ttl_simple.Inout(platform.request("pmt", i))
             self.submodules += phy
-            rtio_channels.append(rtio.Channel(phy.rtlink, ififo_depth=512))
+            rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes,
+                                              ififo_depth=512))
 
         phy = ttl_simple.Inout(platform.request("xtrig", 0))
         self.submodules += phy
-        rtio_channels.append(rtio.Channel(phy.rtlink))
+        rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
 
         for i in range(16):
             phy = ttl_simple.Output(platform.request("ttl", i))
             self.submodules += phy
-            rtio_channels.append(rtio.Channel(phy.rtlink))
+            rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
 
         phy = ttl_simple.Output(platform.request("ext_led", 0))
         self.submodules += phy
-        rtio_channels.append(rtio.Channel(phy.rtlink))
+        rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
 
         for i in range(2, 5):
             phy = ttl_simple.Output(platform.request("user_led", i))
             self.submodules += phy
-            rtio_channels.append(rtio.Channel(phy.rtlink))
+            rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
 
         self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
         self.submodules.dds = RenameClockDomains(
@@ -119,10 +121,11 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
         rtio_channels.append(rtio.Channel(phy.rtlink, ififo_depth=4))
 
         # RTIO core
-        self.submodules.rtiocrg = _RTIOCRG(platform)
+        self.submodules.rtio_crg = _RTIOCRG(platform)
         self.submodules.rtio = rtio.RTIO(rtio_channels,
                                          clk_freq=125000000)
         self.add_constant("RTIO_FINE_TS_WIDTH", self.rtio.fine_ts_width)
+        self.submodules.rtio_mon = rtio.Monitor(rtio_channels)
 
         # CPU connections
         rtio_csrs = self.rtio.get_csrs()