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rtio: fix timestamp shift
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parent
5a2edef422
commit
4e931c7dd2
@ -265,7 +265,7 @@ class LogChannel:
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class Core(Module):
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def __init__(self, channels, full_ts_width=63, guard_io_cycles=20):
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def __init__(self, channels, guard_io_cycles=20):
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data_width = max(rtlink.get_data_width(c.interface)
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for c in channels)
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address_width = max(rtlink.get_address_width(c.interface)
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@ -309,7 +309,7 @@ class Core(Module):
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cmd_reset_phy | ResetSignal("rtio", allow_reset_less=True))
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# Managers
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self.submodules.counter = RTIOCounter(full_ts_width - fine_ts_width)
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self.submodules.counter = RTIOCounter(len(self.cri.o_timestamp) - fine_ts_width)
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i_datas, i_timestamps = [], []
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o_statuses, i_statuses = [], []
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@ -333,10 +333,10 @@ class Core(Module):
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if hasattr(o_manager.ev, "address"):
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self.comb += o_manager.ev.address.eq(self.cri.o_address)
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ts_shift = len(self.cri.o_timestamp) - len(o_manager.ev.timestamp)
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print(n, ts_shift, channel)
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self.comb += o_manager.ev.timestamp.eq(self.cri.o_timestamp[ts_shift:])
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self.comb += o_manager.we.eq(selected &
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(self.cri.cmd == cri.commands["write"]))
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self.comb += o_manager.we.eq(selected & (self.cri.cmd == cri.commands["write"]))
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underflow = Signal()
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sequence_error = Signal()
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@ -372,8 +372,7 @@ class Core(Module):
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else:
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i_datas.append(0)
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if channel.interface.i.timestamped:
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ts_shift = (len(self.cri.i_timestamp)
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- len(i_manager.ev.timestamp))
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ts_shift = (len(self.cri.i_timestamp) - len(i_manager.ev.timestamp))
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i_timestamps.append(i_manager.ev.timestamp << ts_shift)
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else:
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i_timestamps.append(0)
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