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drtio: add TX link layer
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artiq/gateware/drtio/__init__.py
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artiq/gateware/drtio/__init__.py
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artiq/gateware/drtio/link_layer.py
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artiq/gateware/drtio/link_layer.py
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from migen import *
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def K(x, y):
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return (y << 5) | x
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class LinkLayerTX(Module):
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def __init__(self, encoder):
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nwords = len(encoder.k)
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# nwords must be a power of 2
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assert nwords & (nwords - 1) == 0
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self.link_init = Signal()
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self.aux_frame = Signal()
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self.aux_data = Signal(2*nwords)
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self.aux_ack = Signal()
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self.rt_frame = Signal()
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self.rt_data = Signal(8*nwords)
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self.transceiver_data = Signal(10*nwords)
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# # #
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# Idle and auxiliary traffic use special characters excluding
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# K.28.7 and K.29.7 in order to easily separate the link initialization
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# phase (K.28.7 is additionally excluded as we cannot guarantee its
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# non-repetition here).
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# A set of 8 special characters is chosen using a 3-bit control word.
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# This control word is scrambled to reduce EMI. The control words have
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# the following meanings:
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# 100 idle/auxiliary framing
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# 0AB 2 bits of auxiliary data
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aux_scrambler = Scrambler(3*nwords)
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self.submodules += aux_scrambler
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aux_data_ctl = []
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for i in range(nwords):
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aux_data_ctl.append(self.aux_data[i*2:i*2+1])
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aux_data_ctl.append(0)
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self.comb += [
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If(self.aux_frame,
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aux_scrambler.i.eq(Cat(*aux_data_ctl))
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).Else(
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aux_scrambler.i.eq(Replicate(0b100, nwords))
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),
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aux_scrambler.ce.eq(~self.rt_frame),
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self.aux_ack.eq(~self.rt_frame)
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]
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for i in range(nwords):
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scrambled_ctl = scrambler.o[i*3:i*3+3]
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self.sync += [
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encoder.k[i].eq(1),
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If(scrambled_ctl == 7,
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encoder.d[i].eq(K(23, 7))
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).Else(
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encoder.d[i].eq(K(28, scrambled_ctl))
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)
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]
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# Real-time traffic uses data characters and is framed by the special
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# characters of auxiliary traffic. RT traffic is also scrambled.
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rt_scrambler = Scrambler(8*nwords)
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self.submodules += rt_scrambler
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self.comb += rt_scrambler.i.eq(self.rt_data)
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rt_frame_r = Signal()
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self.sync += [
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rt_frame_r.eq(self.rt_frame),
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If(rt_frame_r,
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[k.eq(0) for k in encoder.k],
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[d.eq(self.rt_data[i*8:i*8+8]) for i, d in enumerate(encoder.d)]
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)
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]
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# During link init, send a series of 1*K.28.7 (comma) + 31*K.29.7
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# The receiving end configures its transceiver to also place the comma
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# on its LSB, achieving fixed (or known) latency and alignment of
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# packet starts.
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# K.29.7 is chosen to avoid comma alignment issues arising from K.28.7.
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link_init_r = Signal()
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link_init_counter = Signal(max=32//nwords)
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self.sync += [
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link_init_r.eq(self.link_init),
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If(link_init_r,
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link_init_counter.eq(link_init_counter + 1),
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[k.eq(1) for k in encoder.k],
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[d.eq(K(29, 7)) for d in encoder.d[1:]],
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If(link_init_counter == 0,
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encoder.d[0].eq(K(28, 7)),
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).Else(
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encoder.d[0].eq(K(29, 7)),
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)
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).Else(
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link_init_counter.eq(0)
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)
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]
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