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fir: force dsp48
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@ -65,6 +65,7 @@ class FIR(Module):
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if c == 0 or c in coefficients[i + 1:]:
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continue
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m = Signal((width + shift, True))
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m.attr.add("use_multiplier")
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self.sync += m.eq(c*reduce(add, [
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xj for xj, cj in zip(x[::-1], coefficients) if cj == c
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]))
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@ -108,6 +109,7 @@ class ParallelFIR(Module):
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if c == 0 or c in coefficients[i + 1:]:
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continue
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m = Signal((width + shift, True))
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m.attr.add("use_multiplier")
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self.sync += m.eq(c*reduce(add, [
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xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c
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]))
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@ -169,6 +169,9 @@ class Phaser(MiniSoC, AMPSoC):
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ident=artiq_version,
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**kwargs)
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AMPSoC.__init__(self)
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self.platform.toolchain.attr_translate["use_multiplier"] = \
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("use_dsp48", "yes")
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self.platform.toolchain.bitstream_commands.extend([
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"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
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])
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