mirror of https://github.com/m-labs/artiq.git
drtio: aux controller minor fixes
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parent
84bd962ed5
commit
e1394db861
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@ -1,5 +1,6 @@
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from migen import *
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from migen.fhdl.simplify import FullMemoryWE
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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@ -50,7 +51,7 @@ class Transmitter(Module, AutoCSR):
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frame_counter = Signal(frame_counter_nbits)
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frame_counter_next = Signal(frame_counter_nbits)
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frame_counter_ce = Signal()
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frame_counter_rst = Signal(),
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frame_counter_rst = Signal()
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self.comb += [
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frame_counter_next.eq(frame_counter),
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If(frame_counter_rst,
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@ -68,7 +69,7 @@ class Transmitter(Module, AutoCSR):
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self.submodules += start_tx, tx_done
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self.comb += start_tx.i.eq(self.aux_tx.re)
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self.sync += [
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If(tx_done.o, self.aux_tx_w.eq(0)),
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If(tx_done.o, self.aux_tx.w.eq(0)),
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If(self.aux_tx.re, self.aux_tx.w.eq(1))
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]
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@ -108,7 +109,7 @@ class Receiver(Module, AutoCSR):
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# when continuously drained, the Converter accepts data continuously
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self.sync.rtio_rx += [
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converter.sink.stb.eq(converter.rx_aux_stb),
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converter.sink.stb.eq(link_layer.rx_aux_stb),
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converter.sink.data.eq(link_layer.rx_aux_data)
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]
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self.comb += converter.sink.eop.eq(link_layer.rx_aux_stb & ~link_layer.rx_aux_frame)
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@ -127,7 +128,7 @@ class Receiver(Module, AutoCSR):
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frame_counter.attr.add("no_retiming")
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frame_counter_sys = Signal(frame_counter_nbits)
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self.specials += MultiReg(frame_counter, frame_counter_sys)
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self.comb += aux_rx_length.status.eq(frame_counter_sys << log2_int(mem_dw//8))
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self.comb += self.aux_rx_length.status.eq(frame_counter_sys << log2_int(mem_dw//8))
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signal_frame = PulseSynchronizer("rtio_rx", "sys")
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frame_ack = PulseSynchronizer("sys", "rtio_rx")
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@ -137,7 +138,7 @@ class Receiver(Module, AutoCSR):
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If(self.aux_rx_present.re, self.aux_rx_present.w.eq(0)),
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If(signal_frame.o, self.aux_rx_present.w.eq(1)),
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If(self.aux_rx_error.re, self.aux_rx_error.w.eq(0)),
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If(signal_error.o, self.aux_rx_error.eq(1))
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If(signal_error.o, self.aux_rx_error.w.eq(1))
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]
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self.comb += frame_ack.i.eq(self.aux_rx_present.re)
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@ -202,12 +203,12 @@ class AuxController(Module):
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self.submodules.receiver = Receiver(link_layer, len(self.bus.dat_w))
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# TODO: FullMemoryWE should be applied by migen.build
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tx_sdram_if = FullMemoryWE()(self.transmitter.mem, read_only=False)
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tx_sdram_if = FullMemoryWE()(wishbone.SRAM(self.transmitter.mem, read_only=False))
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rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True)
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wsb = log2_int(len(self.bus.dat_w)//8)
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decoder = wishbone.Decoder(self.bus,
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[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if)
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(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if)],
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[(lambda a: a[log2_int(max_packet)-wsb] == 0, tx_sdram_if.bus),
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(lambda a: a[log2_int(max_packet)-wsb] == 1, rx_sdram_if.bus)],
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register=True)
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self.submodules += tx_sdram_if, rx_sdram_if, decoder
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