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drtio: map local RTIO core on lower channels

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This commit is contained in:
Sebastien Bourdeauducq 2017-02-24 18:15:27 +08:00
parent 623a605d3b
commit 360be0098f
2 changed files with 20 additions and 20 deletions
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38
artiq/examples/drtio/device_db.pyon
View File

@ -21,25 +21,25 @@
"class": "CoreCache"
},
"rled0": {
"led0": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0},
},
"rled1": {
"led1": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 1},
},
"rled2": {
"led2": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 2},
},
"rled3": {
"led3": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
@ -51,94 +51,94 @@
"class": "TTLOut",
"arguments": {"channel": 4},
},
"rled5": {
"led5": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 5},
},
"rled6": {
"led6": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 6},
},
"rled7": {
"led7": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 7},
},
"rsmap": {
"smap": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 8}
},
"rsman": {
"sman": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 9}
},
"led0": {
"rled0": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010000},
},
"led1": {
"rled1": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010001},
},
"led2": {
"rled2": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010002},
},
"led3": {
"rled3": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010003},
},
"led4": {
"rled4": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010004},
},
"led5": {
"rled5": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010005},
},
"led6": {
"rled6": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010006},
},
"led7": {
"rled7": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010007},
},
"smap": {
"rsmap": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 0x010008}
},
"sman": {
"rsman": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",

2
artiq/gateware/targets/kc705_drtio_master.py
View File

@ -113,7 +113,7 @@ class Master(MiniSoC, AMPSoC):
self.register_kernel_cpu_csrdevice("rtio_dma")
self.submodules.cri_con = rtio.CRIInterconnectShared(
[self.rtio.cri, self.rtio_dma.cri],
[self.drtio.cri, self.rtio_core.cri])
[self.rtio_core.cri, self.drtio.cri])
def main():