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rtio: refactor RelaxedAsyncResetSynchronizer
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@ -284,6 +284,18 @@ class LogChannel:
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self.overrides = []
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class _RelaxedAsyncResetSynchronizer(Module):
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def __init__(self, cd, async_reset):
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self.clock_domains.cd_rst = ClockDomain()
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self.clock_domains.cd_no_rst = ClockDomain(reset_less=True)
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self.specials += AsyncResetSynchronizer(self.cd_rst, async_reset)
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self.comb += [
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self.cd_rst.clk.eq(cd.clk),
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self.cd_no_rst.clk.eq(cd.clk),
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]
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self.sync.no_rst += cd.rst.eq(self.cd_rst.rst)
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class Core(Module, AutoCSR):
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def __init__(self, channels, fine_ts_width=None, guard_io_cycles=20):
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if fine_ts_width is None:
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@ -316,28 +328,18 @@ class Core(Module, AutoCSR):
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cmd_reset_phy.attr.add("no_retiming")
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self.clock_domains.cd_rsys = ClockDomain()
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self.clock_domains.cd_rio_rst = ClockDomain()
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self.clock_domains.cd_rio_phy_rst = ClockDomain()
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self.clock_domains.cd_rio_no_rst = ClockDomain()
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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self.comb += [
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self.cd_rsys.clk.eq(ClockSignal()),
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self.cd_rsys.rst.eq(cmd_reset),
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self.cd_rio_rst.clk.eq(ClockSignal("rtio")),
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self.cd_rio_phy_rst.clk.eq(ClockSignal("rtio")),
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self.cd_rio_no_rst.clk.eq(ClockSignal("rtio")),
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self.cd_rio.clk.eq(ClockSignal("rtio")),
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self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
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]
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self.specials += [
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AsyncResetSynchronizer(self.cd_rio_rst, cmd_reset),
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AsyncResetSynchronizer(self.cd_rio_phy_rst, cmd_reset_phy),
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]
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self.sync.rio_no_rst += [
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self.cd_rio.rst.eq(self.cd_rio_rst.rst),
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self.cd_rio_phy.rst.eq(self.cd_rio_phy_rst.rst),
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]
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self.submodules.rars_rio = _RelaxedAsyncResetSynchronizer(
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self.cd_rio, cmd_reset)
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self.submodules.rars_rio_phy = _RelaxedAsyncResetSynchronizer(
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self.cd_rio_phy, cmd_reset_phy)
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# Managers
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self.submodules.counter = RTIOCounter(len(self.cri.timestamp) - fine_ts_width)
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