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drtio: add master gateware target
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71
artiq/gateware/targets/kc705_drtio_master.py
Executable file
71
artiq/gateware/targets/kc705_drtio_master.py
Executable file
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#!/usr/bin/env python3.5
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import argparse
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from migen import *
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from migen.fhdl.specials import Keep
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.soc import AMPSoC, build_artiq_soc
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from artiq.gateware.drtio.transceiver import gtx_7series
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from artiq.gateware.drtio import DRTIOMaster
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from artiq import __version__ as artiq_version
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class Master(MiniSoC, AMPSoC):
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mem_map = {
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"timer_kernel": 0x10000000, # (shadow @0x90000000)
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"drtio": 0x20000000, # (shadow @0xa0000000)
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"mailbox": 0x70000000 # (shadow @0xf0000000)
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}
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mem_map.update(MiniSoC.mem_map)
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def __init__(self, **kwargs):
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MiniSoC.__init__(self,
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cpu_type="or1k",
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sdram_controller_type="minicon",
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l2_size=128*1024,
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with_timer=False,
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ident=artiq_version,
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**kwargs)
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AMPSoC.__init__(self)
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platform = self.platform
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self.comb += platform.request("sfp_tx_disable_n").eq(1)
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self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
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clock_pads=platform.request("sgmii_clock"),
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tx_pads=platform.request("sfp_tx"),
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rx_pads=platform.request("sfp_rx"),
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sys_clk_freq=self.clk_freq,
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clock_div2=True)
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self.submodules.drtio = DRTIOMaster(self.transceiver)
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self.register_kernel_cpu_csrdevice("drtio")
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self.specials += [
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Keep(self.ethphy.crg.cd_eth_rx.clk),
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Keep(self.ethphy.crg.cd_eth_tx.clk),
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]
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platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.)
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platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.)
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platform.add_false_path_constraints(
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self.ethphy.crg.cd_eth_rx.clk,
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self.ethphy.crg.cd_eth_tx.clk)
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def main():
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parser = argparse.ArgumentParser(
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description="ARTIQ with DRTIO on KC705 - Master")
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builder_args(parser)
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soc_kc705_args(parser)
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args = parser.parse_args()
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soc = Master(**soc_kc705_argdict(args))
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build_artiq_soc(soc, builder_argdict(args))
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if __name__ == "__main__":
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main()
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0
artiq/gateware/targets/kc705_drtio_satellite.py
Normal file → Executable file
0
artiq/gateware/targets/kc705_drtio_satellite.py
Normal file → Executable file
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