M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 11:18:27 +08:00
Code Issues Projects Releases Wiki Activity

gateware/rt2wb: support combinatorial ack

Browse Source
This commit is contained in:
Robert Jördens 2016-02-29 15:24:17 +01:00
parent 1b08e65fa1
commit f73228f248
1 changed files with 4 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
artiq/gateware/rtio/phy/wishbone.py
View File

@ -23,6 +23,9 @@ class RT2WB(Module):
active = Signal()
self.sync.rio += [
If(active & wb.ack,
active.eq(0),
),
If(self.rtlink.o.stb,
active.eq(1),
wb.adr.eq(self.rtlink.o.address[:address_width]),
@ -30,15 +33,11 @@ class RT2WB(Module):
wb.dat_w.eq(self.rtlink.o.data),
wb.sel.eq(2**len(wb.sel) - 1)
),
If(wb.ack,
active.eq(0)
)
]
self.comb += [
self.rtlink.o.busy.eq(active),
self.rtlink.o.busy.eq(active & ~wb.ack),
wb.cyc.eq(active),
wb.stb.eq(active),
self.rtlink.i.stb.eq(active & wb.ack & ~wb.we),
self.rtlink.i.data.eq(wb.dat_r)
]