gateware/rt2wb: support combinatorial ack

artiq/gateware/rtio/phy/wishbone.py

@@ -23,6 +23,9 @@ class RT2WB(Module):
 
         active = Signal()
         self.sync.rio += [
+            If(active & wb.ack,
+                active.eq(0),
+            ),
             If(self.rtlink.o.stb,
                 active.eq(1),
                 wb.adr.eq(self.rtlink.o.address[:address_width]),
@@ -30,15 +33,11 @@ class RT2WB(Module):
                 wb.dat_w.eq(self.rtlink.o.data),
                 wb.sel.eq(2**len(wb.sel) - 1)
             ),
-            If(wb.ack,
-                active.eq(0)
-            )
         ]
         self.comb += [
-            self.rtlink.o.busy.eq(active),
+            self.rtlink.o.busy.eq(active & ~wb.ack),
             wb.cyc.eq(active),
             wb.stb.eq(active),
-
             self.rtlink.i.stb.eq(active & wb.ack & ~wb.we),
             self.rtlink.i.data.eq(wb.dat_r)
         ]