moninj: do not require a rsys clock domain

2017-02-20 15:52:48 +08:00 · 2017-02-20 15:52:48 +08:00 · c66efc0279
parent 8da28177a4
commit c66efc0279
1 changed files with 1 additions and 1 deletions
--- a/artiq/gateware/rtio/moninj.py
+++ b/artiq/gateware/rtio/moninj.py
@ -20,7 +20,7 @@ class Monitor(Module, AutoCSR):
        for cp in chan_probes:
            cp_sys = []
            for p in cp:
-                vs = BusSynchronizer(len(p), "rio", "rsys")
+                vs = BusSynchronizer(len(p), "rio", "sys")
                self.submodules += vs
                self.comb += vs.i.eq(p)
                cp_sys.append(vs.o)