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drtio: test replace in RTL simulation

This commit is contained in:
Sebastien Bourdeauducq 2017-04-06 16:33:59 +08:00
parent 729e7b52f0
commit c2667debf8
1 changed files with 3 additions and 2 deletions
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5
artiq/gateware/test/drtio/test_full_stack.py
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@ -143,7 +143,8 @@ class TestFullStack(unittest.TestCase):
delay(200*8)
yield from write(0, 1)
delay(5*8)
yield from write(0, 0)
yield from write(0, 1)
yield from write(0, 0) # replace
yield from write(1, 1)
delay(6*8)
yield from write(1, 0)
@ -159,7 +160,7 @@ class TestFullStack(unittest.TestCase):
self.assertNotEqual((yield dut.phy2.received_data), correct_large_data)
delay(10*8)
yield from write(2, correct_large_data)
for i in range(40):
for i in range(45):
yield
self.assertEqual((yield dut.phy2.received_data), correct_large_data)