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drtio: fix aux receiver, add aux transmitter
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commit
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@ -8,9 +8,89 @@ from misoc.interconnect import wishbone
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max_packet = 1024
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class Transmitter(Module, AutoCSR):
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def __init__(self, link_layer, min_mem_dw):
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# TODO
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self.aux_tx_length = CSRStorage(bits_for(max_packet))
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self.aux_tx = CSR()
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ll_dw = len(link_layer.tx_aux_data)
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mem_dw = max(min_mem_dw, ll_dw)
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self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8))
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converter = stream.Converter(mem_dw, ll_dw)
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self.submodules += converter
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# when continuously fed, the Converter outputs data continuously
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self.comb += [
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converter.source.ack.eq(link_layer.tx_aux_ack),
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link_layer.tx_aux_frame.eq(converter.source.stb),
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link_layer.tx_aux_data.eq(converter.source.data)
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]
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seen_eop_rst = Signal()
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frame_r = Signal()
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seen_eop = Signal()
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self.sync.rtio += [
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If(link_layer.tx_aux_ack,
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frame_r.eq(link_layer.tx_aux_frame),
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If(frame_r & ~link_layer.tx_aux_frame, seen_eop.eq(1))
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),
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If(seen_eop_rst, seen_eop.eq(0))
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]
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mem_port = self.mem.get_port(clock_domain="rtio")
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self.specials += mem_port
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self.aux_tx_length.storage.attr.add("no_retiming")
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tx_length = Signal(bits_for(max_packet))
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self.specials += MultiReg(self.aux_tx_length.storage, tx_length, "rtio")
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frame_counter_nbits = bits_for(max_packet) - log2_int(mem_dw//8)
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frame_counter = Signal(frame_counter_nbits)
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frame_counter_next = Signal(frame_counter_nbits)
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frame_counter_ce = Signal()
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frame_counter_rst = Signal(),
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self.comb += [
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frame_counter_next.eq(frame_counter),
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If(frame_counter_rst,
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frame_counter_next.eq(0)
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).Elif(frame_counter_ce,
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frame_counter_next.eq(frame_counter + 1)
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),
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mem_port.adr.eq(frame_counter_next),
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converter.sink.data.eq(mem_port.dat_r)
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]
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self.sync.rtio += frame_counter.eq(frame_counter_next)
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start_tx = PulseSynchronizer("sys", "rtio")
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tx_done = PulseSynchronizer("rtio", "sys")
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self.submodules += start_tx, tx_done
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self.comb += start_tx.i.eq(self.aux_tx.re)
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self.sync += [
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If(tx_done.o, self.aux_tx_w.eq(0)),
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If(self.aux_tx.re, self.aux_tx.w.eq(1))
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]
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fsm = ClockDomainsRenamer("rtio")(FSM(reset_state="IDLE"))
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self.submodules += fsm
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fsm.act("IDLE",
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frame_counter_rst.eq(1),
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seen_eop_rst.eq(1),
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If(start_tx.o, NextState("TRANSMIT"))
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)
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fsm.act("TRANSMIT",
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converter.sink.stb.eq(1),
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frame_counter_ce.eq(1),
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If(frame_counter_next == tx_length, NextState("WAIT_INTERFRAME"))
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)
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fsm.act("WAIT_INTERFRAME",
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If(seen_eop,
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tx_done.i.eq(1),
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NextState("IDLE")
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)
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)
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class Receiver(Module, AutoCSR):
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@ -26,11 +106,12 @@ class Receiver(Module, AutoCSR):
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converter = stream.Converter(ll_dw, mem_dw)
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self.submodules += converter
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# when continuously drained, the Converter accepts data continuously
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self.sync.rtio_rx += [
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converter.sink.stb.eq(link_layer.rx_aux_frame),
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converter.sink.stb.eq(converter.rx_aux_stb),
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converter.sink.data.eq(link_layer.rx_aux_data)
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]
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self.comb += converter.sink.eop.eq(~link_layer.rx_aux_frame)
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self.comb += converter.sink.eop.eq(link_layer.rx_aux_stb & ~link_layer.rx_aux_frame)
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mem_port = self.mem.get_port(write_capable=True, clock_domain="rtio_rx")
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self.specials += mem_port
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@ -39,7 +120,8 @@ class Receiver(Module, AutoCSR):
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frame_counter = Signal(frame_counter_nbits)
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self.comb += [
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mem_port.adr.eq(frame_counter),
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mem_port.dat_w.eq(link_layer.rx_aux_data)
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mem_port.dat_w.eq(converter.source.data),
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converter.source.ack.eq(1)
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]
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frame_counter.attr.add("no_retiming")
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@ -62,38 +144,54 @@ class Receiver(Module, AutoCSR):
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fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="IDLE"))
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self.submodules += fsm
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rx_aux_frame_r = Signal()
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self.sync.rtio_rx += rx_aux_frame_r.eq(link_layer.rx_aux_frame)
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sop = Signal()
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self.sync.rtio_rx += \
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If(converter.source.stb,
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If(converter.source.eop,
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sop.eq(1)
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).Else(
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sop.eq(0)
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)
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)
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fsm.act("IDLE",
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If(link_layer.rx_aux_frame & ~rx_aux_frame_r,
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If(converter.source.stb & sop,
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NextValue(frame_counter, frame_counter + 1),
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mem_port.we.eq(1),
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NextState("FRAME")
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If(converter.source.eop,
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NextState("SIGNAL_FRAME")
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).Else(
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NextState("FRAME")
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)
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).Else(
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NextValue(frame_counter, 0)
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)
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)
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fsm.act("FRAME",
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If(link_layer.rx_aux_frame,
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If(converter.source.stb,
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NextValue(frame_counter, frame_counter + 1),
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mem_port.we.eq(1),
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If(frame_counter == max_packet,
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mem_port.we.eq(0),
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signal_error.i.eq(1),
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NextState("IDLE") # remainder of the frame discarded
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NextState("IDLE") # discard the rest of the frame
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),
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If(converter.source.eop,
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NextState("SIGNAL_FRAME")
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)
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).Else(
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signal_frame.i.eq(1),
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NextState("WAIT_ACK")
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)
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)
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fsm.act("SIGNAL_FRAME",
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signal_frame.i.eq(1),
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NextState("WAIT_ACK"),
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If(converter.source.stb, signal_error.i.eq(1))
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)
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fsm.act("WAIT_ACK",
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If(frame_ack.o,
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NextValue(frame_counter, 0),
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NextState("IDLE")
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),
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If(link_layer.rx_aux_frame, signal_error.i.eq(1))
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If(converter.source.stb, signal_error.i.eq(1))
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)
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