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mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 03:08:27 +08:00

runtime: report TTL status over UDP

This commit is contained in:
Sebastien Bourdeauducq 2015-06-03 18:26:19 +08:00
parent e5f16b29fd
commit a2ae5e4706
9 changed files with 98 additions and 4 deletions

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@ -1,2 +1,2 @@
from artiq.gateware.rtio.core import Channel, RTIO
from artiq.gateware.rtio.monitor import Monitor
from artiq.gateware.rtio.moninj import Monitor

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@ -2,6 +2,7 @@ from migen.fhdl.std import *
from migen.bank.description import *
from migen.genlib.cdc import BusSynchronizer
class Monitor(Module, AutoCSR):
def __init__(self, channels):
chan_probes = [c.probes for c in channels]

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@ -1,6 +1,6 @@
include $(MSCDIR)/software/common.mak
OBJECTS := isr.o flash_storage.o clock.o elf_loader.o services.o session.o log.o test_mode.o kloader.o bridge_ctl.o mailbox.o ksupport_data.o kserver.o main.o
OBJECTS := isr.o flash_storage.o clock.o elf_loader.o services.o session.o log.o test_mode.o kloader.o bridge_ctl.o mailbox.o ksupport_data.o kserver.o moninj.o main.o
OBJECTS_KSUPPORT := ksupport.o exception_jmp.o exceptions.o mailbox.o bridge.o rtio.o ttl.o dds.o
CFLAGS += -Ilwip/src/include -Iliblwip

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@ -66,7 +66,7 @@ a lot of data that needs to be copied, this should be set high. */
#define MEMP_NUM_PBUF 64
/* MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
per active UDP "connection". */
#define MEMP_NUM_UDP_PCB 1
#define MEMP_NUM_UDP_PCB 2
/* MEMP_NUM_TCP_PCB: the number of simulatenously active TCP
connections. */
#define MEMP_NUM_TCP_PCB 8
@ -159,7 +159,7 @@ a lot of data that needs to be copied, this should be set high. */
#define DHCP_DOES_ARP_CHECK 0
/* ---------- UDP options ---------- */
#define LWIP_UDP 0
#define LWIP_UDP 1
#define UDP_TTL 255

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@ -28,6 +28,7 @@
#include "test_mode.h"
#include "kserver.h"
#include "session.h"
#include "moninj.h"
static void common_init(void)
{
@ -139,6 +140,7 @@ static void regular_main(void)
puts("Accepting sessions on Ethernet.");
network_init();
kserver_init();
moninj_init();
session_end();
while(1) {

83
soc/runtime/moninj.c Normal file
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@ -0,0 +1,83 @@
#include <generated/csr.h>
#ifdef CSR_ETHMAC_BASE
#include <netif/etharp.h>
#include <lwip/init.h>
#include <lwip/memp.h>
#include <lwip/ip4_addr.h>
#include <lwip/ip4.h>
#include <lwip/netif.h>
#include <lwip/sys.h>
#include <lwip/udp.h>
#include <lwip/timers.h>
#include "log.h"
#include "moninj.h"
enum {
MONINJ_REQ_MONITOR = 1
};
static struct udp_pcb *listen_pcb;
struct monitor_reply {
long long int ttl_levels;
long long int ttl_oes;
};
static void moninj_monitor(const ip_addr_t *addr, u16_t port)
{
struct monitor_reply reply;
int i;
struct pbuf *reply_p;
reply.ttl_levels = 0;
reply.ttl_oes = 0;
for(i=0;i<RTIO_TTL_COUNT;i++) {
rtio_mon_chan_sel_write(i);
rtio_mon_probe_sel_write(0);
if(rtio_mon_probe_value_read())
reply.ttl_levels |= 1LL << i;
rtio_mon_probe_sel_write(1);
if(rtio_mon_probe_value_read())
reply.ttl_oes |= 1LL << i;
}
reply_p = pbuf_alloc(PBUF_TRANSPORT, sizeof(struct monitor_reply), PBUF_RAM);
if(!reply_p) {
log("Failed to allocate pbuf for monitor reply");
return;
}
memcpy(reply_p->payload, &reply, sizeof(struct monitor_reply));
udp_sendto(listen_pcb, reply_p, addr, port);
pbuf_free(reply_p);
}
static void moninj_recv(void *arg, struct udp_pcb *upcb, struct pbuf *req,
const ip_addr_t *addr, u16_t port)
{
if(req->len >= 1) {
switch(*(char *)req->payload) {
case MONINJ_REQ_MONITOR:
moninj_monitor(addr, port);
break;
default:
break;
}
}
pbuf_free(req); /* beware: addr may point into the req pbuf */
}
void moninj_init(void)
{
listen_pcb = udp_new();
if(!listen_pcb) {
log("Failed to create UDP listening PCB");
return;
}
udp_bind(listen_pcb, IP_ADDR_ANY, 3250);
udp_recv(listen_pcb, moninj_recv, NULL);
}
#endif /* CSR_ETHMAC_BASE */

6
soc/runtime/moninj.h Normal file
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@ -0,0 +1,6 @@
#ifndef __MONINJ_H
#define __MONINJ_H
void moninj_init(void);
#endif /* __MONINJ_H */

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@ -76,6 +76,7 @@ class NIST_QC1(MiniSoC, AMPSoC):
phy = ttl_simple.Output(platform.request("user_led", 2))
self.submodules += phy
rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
self.submodules.dds = RenameClockDomains(

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@ -111,6 +111,7 @@ trce -v 12 -fastpaths -tsi {build_name}.tsi -o {build_name}.twr {build_name}.ncd
phy = ttl_simple.Output(platform.request("user_led", i))
self.submodules += phy
rtio_channels.append(rtio.Channel(phy.rtlink, phy.probes))
self.add_constant("RTIO_TTL_COUNT", len(rtio_channels))
self.add_constant("RTIO_DDS_CHANNEL", len(rtio_channels))
self.submodules.dds = RenameClockDomains(