mirror of https://github.com/m-labs/artiq.git
phaser: tag jesd as clock net
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4ea3dea217
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@ -458,6 +458,7 @@ class AD9154JESD(Module, AutoCSR):
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Instance("BUFG", i_I=self.refclk, o_O=self.cd_jesd.clk),
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AsyncResetSynchronizer(self.cd_jesd, ResetSignal("rio_phy")),
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]
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platform.add_period_constraint(self.cd_jesd.clk, 1e9/refclk_freq)
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qpll = GTXQuadPLL(self.refclk, refclk_freq, linerate)
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self.submodules += qpll
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@ -467,8 +468,8 @@ class AD9154JESD(Module, AutoCSR):
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qpll, platform.request("ad9154_jesd", i), fabric_freq)
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platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate)
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self.comb += phy.gtx.gtx_init.bypass_phalign.eq(1) # TODO
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for clk in self.cd_jesd.clk, refclk_pads.p, self.refclk:
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platform.add_false_path_constraints(clk, phy.gtx.cd_tx.clk)
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platform.add_false_path_constraints(self.cd_jesd.clk,
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phy.gtx.cd_tx.clk)
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phys.append(phy)
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to_jesd = ClockDomainsRenamer("jesd")
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self.submodules.core = to_jesd(JESD204BCoreTX(phys, settings,
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