M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-25 03:08:27 +08:00
Code Issues Projects Releases Wiki Activity

sawg: reduce coefficient width

Browse Source
This commit is contained in:
Robert Jördens 2016-12-08 16:14:32 +01:00
parent 598da09a93
commit 18e3f58c22
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
artiq/gateware/dsp/sawg.py
View File

@ -146,9 +146,9 @@ class Channel(Module, SatAddMixin):
self.submodules.a1 = a1 = SplineParallelDDS(widths, orders)
self.submodules.a2 = a2 = SplineParallelDDS(widths, orders)
coeff = [[int(round((1 << 26) * ci)) for ci in c]
coeff = [[int(round((1 << 18)*ci)) for ci in c]
for c in halfgen4_cascade(parallelism, width=.4, order=8)]
hbf = [ParallelHBFUpsampler(coeff, width=width, shift=25)
hbf = [ParallelHBFUpsampler(coeff, width=width, shift=17)
for i in range(2)]
self.submodules.b = b = SplineParallelDUC(
widths._replace(a=len(a1.xo[0]), f=widths.f - width), orders,