mirror of https://github.com/m-labs/artiq.git
analyzer: fix byte_count
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@ -167,11 +167,9 @@ class DMAWriter(Module, AutoCSR):
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alignment_bits=data_alignment)
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self.byte_count = CSRStatus(32) # only read when shut down
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sink_layout = [("data", dw)]
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if messages_per_dw > 1:
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sink_layout.append(("valid_token_count",
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bits_for(messages_per_dw)))
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self.sink = stream.Endpoint(sink_layout)
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self.sink = stream.Endpoint(
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[("data", dw),
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("valid_token_count", bits_for(messages_per_dw))])
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# # #
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@ -201,12 +199,13 @@ class DMAWriter(Module, AutoCSR):
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)
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]
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event_counter = Signal(32)
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message_count = Signal(32 - log2_int(message_len))
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self.comb += self.byte_count.status.eq(
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event_counter << data_alignment)
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message_count << log2_int(message_len))
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self.sync += [
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If(self.reset.re, event_counter.eq(0)),
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If(membus.ack, event_counter.eq(event_counter + 1))
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If(self.reset.re, message_count.eq(0)),
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If(membus.ack, message_count.eq(
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message_count + self.sink.valid_token_count))
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]
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@ -220,10 +219,9 @@ class Analyzer(Module, AutoCSR):
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rtio_core, self.enable.storage)
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self.submodules.fifo = stream.SyncFIFO(
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[("data", message_len)], fifo_depth, True)
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dw = len(membus.dat_w)
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self.submodules.converter = stream.Converter(
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message_len, dw, reverse=True,
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report_valid_token_count=dw > message_len)
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message_len, len(membus.dat_w), reverse=True,
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report_valid_token_count=True)
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self.submodules.dma = DMAWriter(membus)
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enable_r = Signal()
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