mirror of https://github.com/m-labs/artiq.git
phaser: support core stpl
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@ -42,6 +42,11 @@ def ad9154_jesd_prbs(prbs: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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@syscall(flags={"nounwind", "nowrite"})
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def ad9154_jesd_stpl(prbs: TInt32) -> TNone:
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raise NotImplementedError("syscall not simulated")
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class AD9154:
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"""AD9154-FMC-EBZ SPI support
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@ -95,3 +100,7 @@ class AD9154:
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@kernel
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def jesd_prbs(self, prbs):
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ad9154_jesd_prbs(prbs)
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@kernel
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def jesd_stpl(self, enable):
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ad9154_jesd_stpl(enable)
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@ -544,15 +544,6 @@ class Phaser(_NIST_Ions):
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# while at 5 GBps, take every second sample... FIXME
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self.comb += conv.eq(Cat(ch.o[::2]))
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if False:
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# short transport layer test pattern
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self.comb += [
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self.ad9154.jesd_core.transport.sink.converter0.eq(0x01230123),
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self.ad9154.jesd_core.transport.sink.converter1.eq(0x45674567),
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self.ad9154.jesd_core.transport.sink.converter2.eq(0x89ab89ab),
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self.ad9154.jesd_core.transport.sink.converter3.eq(0xcdefcdef)
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]
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self.comb += jesd_sync.eq(self.ad9154.jesd_sync)
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@ -69,4 +69,9 @@ void ad9154_jesd_prbs(int p)
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ad9154_jesd_control_prbs_config_write(p);
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}
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void ad9154_jesd_stpl(int en)
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{
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ad9154_jesd_control_stpl_enable_write(en);
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}
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#endif /* CONFIG_AD9154_DAC_CS */
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@ -13,6 +13,7 @@ uint8_t ad9516_read(uint16_t addr);
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void ad9154_jesd_enable(int en);
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int ad9154_jesd_ready(void);
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void ad9154_jesd_prbs(int p);
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void ad9154_jesd_stpl(int en);
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#endif
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#endif
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@ -147,6 +147,7 @@ static const struct symbol runtime_exports[] = {
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{"ad9154_jesd_enable", &ad9154_jesd_enable},
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{"ad9154_jesd_ready", &ad9154_jesd_ready},
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{"ad9154_jesd_prbs", &ad9154_jesd_prbs},
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{"ad9154_jesd_stpl", &ad9154_jesd_stpl},
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#endif
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/* end */
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