M-Labs/artiq
2
0
Fork 2
mirror of https://github.com/m-labs/artiq.git synced 2024-12-26 11:48:27 +08:00
Code Issues Projects Releases Wiki Activity

rtio/sed: rename fifos/gates, refactor tsc

Browse Source
This commit is contained in:
Sebastien Bourdeauducq 2017-09-16 14:03:48 +08:00
parent ac52c7c818
commit 92c63ce2e4
2 changed files with 14 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
artiq/gateware/rtio/sed/fifo.py → artiq/gateware/rtio/sed/fifos.py
View File

@ -4,21 +4,21 @@ from migen.genlib.fifo import *
from artiq.gateware.rtio.sed import layouts
__all__ = ["FIFO"]
__all__ = ["FIFOs"]
class FIFO(Module):
def __init__(self, lane_count, mode, fifo_depth, layout_payload):
seqn_width = layouts.seqn_width(lane_count, fifo_width)
self.input = [layouts.fifo_ingress(seqn_width, layout_payload)
class FIFOs(Module):
def __init__(self, lane_count, fifo_depth, layout_payload, mode):
seqn_width = layouts.seqn_width(lane_count, fifo_depth)
self.input = [Record(layouts.fifo_ingress(seqn_width, layout_payload))
for _ in range(lane_count)]
self.output = [layouts.fifo_egress(seqn_width, layout_payload)
self.output = [Record(layouts.fifo_egress(seqn_width, layout_payload))
for _ in range(lane_count)]
if mode == "sync":
fifo_cls = fifo.SyncFIFOBuffered
fifo_cls = SyncFIFOBuffered
elif mode == "async":
fifo_cls = fifo.AsyncFIFO
fifo_cls = AsyncFIFO
else:
raise ValueError

14
artiq/gateware/rtio/sed/tsc_gate.py → artiq/gateware/rtio/sed/gates.py
View File

@ -3,10 +3,10 @@ from migen import *
from artiq.gateware.rtio.sed import layouts
__all__ = ["TSCGate"]
__all__ = ["Gates"]
class TSCGate(Module):
class Gates(Module):
def __init__(self, lane_count, seqn_width, layout_fifo_payload, layout_output_network_payload):
self.input = [Record(layouts.fifo_egress(seqn_width, layout_fifo_payload))
for _ in range(lane_count)]
@ -17,12 +17,11 @@ class TSCGate(Module):
fine_ts_width = len(self.output[0].fine_ts)
else:
fine_ts_width = 0
self.tsc = Signal(64-fine_ts_width)
self.coarse_timestamp = Signal(64-fine_ts_width)
# # #
self.sync += self.tsc.eq(self.tsc + 1)
for input, output in zip(self.input, self.output):
for field, _ in output.payload.layout:
if field == "fine_ts":
@ -32,6 +31,5 @@ class TSCGate(Module):
self.sync += output.seqn.eq(input.seqn)
self.comb += output.replace_occured.eq(0)
self.comb += input.re.eq(input.payload.timestamp[fine_ts_width:] == self.tsc)
self.sync += ouput.valid.eq(input.re & input.readable)
self.comb += input.re.eq(input.payload.timestamp[fine_ts_width:] == self.coarse_timestamp)
self.sync += output.valid.eq(input.re & input.readable)