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use new Migen signal attribute API

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This commit is contained in:
Sebastien Bourdeauducq 2016-10-29 21:17:13 +08:00
parent 6872017449
commit ed4d57c638
2 changed files with 6 additions and 11 deletions
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6
artiq/gateware/rtio/core.py
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@ -24,10 +24,8 @@ class _GrayCodeTransfer(Module):
self.sync.rtio += value_gray_rtio.eq(self.i ^ self.i[1:])
# transfer to system clock domain
value_gray_sys = Signal(width)
self.specials += [
NoRetiming(value_gray_rtio),
MultiReg(value_gray_rtio, value_gray_sys)
]
value_gray_rtio.attr.add("no_retiming")
self.specials += MultiReg(value_gray_rtio, value_gray_sys)
# convert back to binary
value_sys = Signal(width)
self.comb += value_sys[-1].eq(value_gray_sys[-1])

11
artiq/gateware/targets/kc705.py
View File

@ -8,7 +8,6 @@ from migen.genlib.cdc import MultiReg
from migen.build.generic_platform import *
from migen.build.xilinx.vivado import XilinxVivadoToolchain
from migen.build.xilinx.ise import XilinxISEToolchain
from migen.fhdl.specials import Keep
from misoc.interconnect.csr import *
from misoc.interconnect import wishbone
@ -147,12 +146,10 @@ class _NIST_Ions(MiniSoC, AMPSoC):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.specials += [
Keep(self.rtio.cd_rsys.clk),
Keep(self.rtio_crg.cd_rtio.clk),
Keep(self.ethphy.crg.cd_eth_rx.clk),
Keep(self.ethphy.crg.cd_eth_tx.clk),
]
self.rtio.cd_rsys.clk.attr.add("keep")
self.rtio_crg.cd_rtio.clk.attr.add("keep")
self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
self.platform.add_period_constraint(self.rtio.cd_rsys.clk, 8.)
self.platform.add_period_constraint(self.rtio_crg.cd_rtio.clk, 8.)