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drtio: multilink transceiver interface
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@ -9,6 +9,22 @@ from artiq.gateware.drtio import (link_layer, aux_controller,
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rt_packet_master, rt_controller_master)
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class ChannelInterface:
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def __init__(self, encoder, decoders):
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self.rx_ready = Signal()
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self.encoder = encoder
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self.decoders = decoders
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class TransceiverInterface:
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def __init__(self, channel_interfaces):
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self.clock_domains.cd_rtio = ClockDomain()
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for i in range(len(channel_interfaces)):
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name = "rtio_rx" + str(i)
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setattr(self.clock_domains, "cd_"+name, ClockDomain(name=name))
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self.channels = channel_interfaces
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class GenericRXSynchronizer(Module):
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"""Simple RX synchronizer based on the portable Migen elastic buffer.
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@ -33,14 +49,14 @@ class GenericRXSynchronizer(Module):
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class DRTIOSatellite(Module):
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def __init__(self, transceiver, channels, rx_synchronizer=None, fine_ts_width=3, full_ts_width=63):
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def __init__(self, chanif, channels, rx_synchronizer=None, fine_ts_width=3, full_ts_width=63):
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if rx_synchronizer is None:
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rx_synchronizer = GenericRXSynchronizer()
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self.submodules += rx_synchronizer
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self.submodules.link_layer = link_layer.LinkLayer(
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transceiver.encoder, transceiver.decoders)
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self.comb += self.link_layer.rx_ready.eq(transceiver.rx_ready)
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chanif.encoder, chanif.decoders)
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self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
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link_layer_sync = SimpleNamespace(
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tx_aux_frame=self.link_layer.tx_aux_frame,
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@ -85,10 +101,10 @@ class DRTIOSatellite(Module):
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class DRTIOMaster(Module):
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def __init__(self, transceiver, channel_count=1024, fine_ts_width=3):
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def __init__(self, chanif, channel_count=1024, fine_ts_width=3):
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self.submodules.link_layer = link_layer.LinkLayer(
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transceiver.encoder, transceiver.decoders)
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self.comb += self.link_layer.rx_ready.eq(transceiver.rx_ready)
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chanif.encoder, chanif.decoders)
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self.comb += self.link_layer.rx_ready.eq(chanif.rx_ready)
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self.submodules.link_stats = link_layer.LinkLayerStats(self.link_layer, "rtio_rx")
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self.submodules.rt_packet = rt_packet_master.RTPacketMaster(self.link_layer)
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@ -4,22 +4,26 @@ from migen.genlib.resetsync import AsyncResetSynchronizer
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from misoc.cores.code_8b10b import Encoder, Decoder
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from misoc.interconnect.csr import *
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from artiq.gateware.drtio.core import TransceiverInterface, ChannelInterface
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from artiq.gateware.drtio.transceiver.gtx_7series_init import *
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class GTX_20X(Module):
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class GTX_20X(Module, TransceiverInterface):
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# Only one channel is supported.
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#
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# The transceiver clock on clock_pads must be at the RTIO clock
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# frequency when clock_div2=False, and 2x that frequency when
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# clock_div2=True.
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def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq,
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clock_div2=False):
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self.submodules.encoder = ClockDomainsRenamer("rtio")(
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encoder = ClockDomainsRenamer("rtio")(
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Encoder(2, True))
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self.decoders = [ClockDomainsRenamer("rtio_rx")(
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Decoder(True)) for _ in range(2)]
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self.submodules += self.decoders
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self.submodules += encoder
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decoders = [ClockDomainsRenamer("rtio_rx0")(
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(Decoder(True))) for _ in range(2)]
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self.submodules += decoders
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self.rx_ready = Signal()
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TransceiverInterface.__init__(self, [ChannelInterface(encoder, decoders)])
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# transceiver direct clock outputs
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# useful to specify clock constraints in a way palatable to Vivado
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@ -137,8 +141,8 @@ class GTX_20X(Module):
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i_RXSYSCLKSEL=0b00,
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i_RXOUTCLKSEL=0b010,
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o_RXOUTCLK=self.rxoutclk,
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i_RXUSRCLK=ClockSignal("rtio_rx"),
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i_RXUSRCLK2=ClockSignal("rtio_rx"),
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i_RXUSRCLK=ClockSignal("rtio_rx0"),
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i_RXUSRCLK2=ClockSignal("rtio_rx0"),
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p_RXCDR_CFG=0x03000023FF10100020,
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# RX Clock Correction Attributes
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@ -165,7 +169,6 @@ class GTX_20X(Module):
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tx_reset_deglitched = Signal()
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tx_reset_deglitched.attr.add("no_retiming")
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self.sync += tx_reset_deglitched.eq(~tx_init.done)
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self.clock_domains.cd_rtio = ClockDomain()
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self.specials += [
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Instance("BUFG", i_I=self.txoutclk, o_O=self.cd_rtio.clk),
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AsyncResetSynchronizer(self.cd_rtio, tx_reset_deglitched)
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@ -173,24 +176,25 @@ class GTX_20X(Module):
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rx_reset_deglitched = Signal()
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rx_reset_deglitched.attr.add("no_retiming")
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self.sync.rtio += rx_reset_deglitched.eq(~rx_init.done)
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self.clock_domains.cd_rtio_rx = ClockDomain()
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self.specials += [
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Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_rtio_rx.clk),
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AsyncResetSynchronizer(self.cd_rtio_rx, rx_reset_deglitched)
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Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_rtio_rx0.clk),
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AsyncResetSynchronizer(self.cd_rtio_rx0, rx_reset_deglitched)
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]
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chan = self.channels[0]
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self.comb += [
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txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1])),
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self.decoders[0].input.eq(rxdata[:10]),
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self.decoders[1].input.eq(rxdata[10:])
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txdata.eq(Cat(chan.encoder.output[0], chan.encoder.output[1])),
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chan.decoders[0].input.eq(rxdata[:10]),
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chan.decoders[1].input.eq(rxdata[10:])
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]
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clock_aligner = BruteforceClockAligner(0b0101111100, self.rtio_clk_freq)
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clock_aligner = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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BruteforceClockAligner(0b0101111100, self.rtio_clk_freq))
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self.submodules += clock_aligner
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self.comb += [
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clock_aligner.rxdata.eq(rxdata),
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rx_init.restart.eq(clock_aligner.restart),
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self.rx_ready.eq(clock_aligner.ready)
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chan.rx_ready.eq(clock_aligner.ready)
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]
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@ -199,7 +203,7 @@ class GTX_1000BASE_BX10(GTX_20X):
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class RXSynchronizer(Module, AutoCSR):
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"""Delays the data received in the rtio_rx by a configurable amount
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"""Delays the data received in the rtio_rx domain by a configurable amount
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so that it meets s/h in the rtio domain, and recapture it in the rtio
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domain. This has fixed latency.
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@ -53,7 +53,8 @@ class Master(MiniSoC, AMPSoC):
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sys_clk_freq=self.clk_freq,
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clock_div2=True)
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self.submodules.drtio0 = DRTIOMaster(self.transceiver)
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self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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DRTIOMaster(self.transceiver.channels[0]))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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@ -69,7 +70,7 @@ class Master(MiniSoC, AMPSoC):
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self.csr_devices.append("converter_spi")
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self.comb += [
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platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")),
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platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
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platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
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]
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@ -54,11 +54,12 @@ class Satellite(BaseSoC):
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tx_pads=platform.request("sfp_tx"),
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rx_pads=platform.request("sfp_rx"),
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sys_clk_freq=self.clk_freq)
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self.submodules.rx_synchronizer = gtx_7series.RXSynchronizer(
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self.transceiver.rtio_clk_freq, initial_phase=180.0)
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self.submodules.drtio0 = DRTIOSatellite(
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self.transceiver, rtio_channels, self.rx_synchronizer)
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self.csr_devices.append("rx_synchronizer")
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rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
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self.submodules.rx_synchronizer0 = rx0(gtx_7series.RXSynchronizer(
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self.transceiver.rtio_clk_freq, initial_phase=180.0))
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self.submodules.drtio0 = rx0(DRTIOSatellite(
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self.transceiver.channels[0], rtio_channels, self.rx_synchronizer0))
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self.csr_devices.append("rx_synchronizer0")
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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@ -71,7 +72,7 @@ class Satellite(BaseSoC):
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si5324_clkin = platform.request("si5324_clkin")
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self.specials += \
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Instance("OBUFDS",
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i_I=ClockSignal("rtio_rx"),
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i_I=ClockSignal("rtio_rx0"),
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o_O=si5324_clkin.p, o_OB=si5324_clkin.n
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)
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self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
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@ -89,7 +90,7 @@ class Satellite(BaseSoC):
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self.csr_devices.append("converter_spi")
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self.comb += [
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platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx")),
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platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
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platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
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]
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