phaser: cap phy data width to 64 temporarily

2016-11-18 15:46:59 +01:00 · 2016-11-18 15:46:59 +01:00 · 342b9e977e
parent 7664b226f2
commit 342b9e977e
1 changed files with 2 additions and 1 deletions
--- a/artiq/gateware/rtio/phy/sawg.py
+++ b/artiq/gateware/rtio/phy/sawg.py
@ -16,7 +16,8 @@ class Channel(_ChannelPHY):
        _ChannelPHY.__init__(self, *args, **kwargs)
        self.phys = []
        for i in self.i:
-            rl = rtlink.Interface(rtlink.OInterface(len(i.payload)))
+            rl = rtlink.Interface(rtlink.OInterface(
+                min(64, len(i.payload))))  # FIXME
            self.comb += [
                i.stb.eq(rl.o.stb),
                rl.o.busy.eq(~i.ack),