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spi: give wb-reads a register level
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@ -303,9 +303,6 @@ class SPIMaster(Module):
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data_write = Signal.like(spi.reg.data)
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self.comb += [
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bus.dat_r.eq(
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Array([data_read, xfer.raw_bits(), config.raw_bits()
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])[bus.adr]),
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spi.start.eq(pending & (~spi.cs | spi.done)),
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spi.clk_phase.eq(config.clk_phase),
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spi.reg.lsb.eq(config.lsb_first),
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@ -330,6 +327,11 @@ class SPIMaster(Module):
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# d) writing to data register and pending and swapping buffers
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bus.ack.eq(bus.cyc & bus.stb &
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(~bus.we | (bus.adr != 0) | ~pending | spi.done)),
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If(bus.cyc & bus.stb,
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bus.dat_r.eq(
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Array([data_read, xfer.raw_bits(), config.raw_bits()
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])[bus.adr]),
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),
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If(bus.ack,
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bus.ack.eq(0),
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If(bus.we,
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