mirror of https://github.com/m-labs/artiq.git
dsp: implement sawg features
This commit is contained in:
parent
98193d6fa1
commit
51f23feeac
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@ -1,354 +1,176 @@
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from collections import namedtuple
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from migen import *
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from misoc.interconnect.stream import Endpoint
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from misoc.cores.cordic import Cordic
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from .accu import PhasedAccu, Accu
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from .tools import eqh, Delay
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from .tools import eqh, Delay, SatAddMixin
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from .spline import Spline
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class DDSFast(Module):
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def __init__(self, width, parallelism=4):
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a_width = width
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p_width = width
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f_width = 2*width
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_Widths = namedtuple("_Widths", "t a p f")
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_Orders = namedtuple("_Orders", "a p f")
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self.o = [Signal((width, True)) for i in range(parallelism)]
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self.width = width
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class ParallelDDS(Module):
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def __init__(self, widths, parallelism=1, a_delay=0):
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self.i = Endpoint([("x", widths.a), ("y", widths.a),
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("f", widths.f), ("p", widths.f), ("clr", 1)])
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self.parallelism = parallelism
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self.latency = 1 # will be accumulated
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q = PhasedAccu(f_width, parallelism)
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self.submodules += q
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self.latency += q.latency
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self.a = Endpoint([("a", a_width)])
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self.f = Endpoint([("f", f_width)])
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self.p = Endpoint([("p", p_width)])
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self.i = [self.a, self.f, self.p]
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self.widths = widths
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###
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a = Signal.like(self.a.a)
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self.sync += [
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If(self.a.stb,
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a.eq(self.a.a)
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),
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If(self.f.stb,
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eqh(q.i.f, self.f.f)
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),
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q.i.clr.eq(0),
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If(self.p.stb,
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eqh(q.i.p, self.p.p),
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q.i.clr.eq(1)
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),
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q.i.stb.eq(self.f.stb | self.p.stb),
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]
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accu = PhasedAccu(widths.f, parallelism)
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cordic = [Cordic(width=widths.a, widthz=widths.p, guard=None,
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eval_mode="pipelined") for i in range(parallelism)]
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self.xo = [c.xo for c in cordic]
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self.yo = [c.yo for c in cordic]
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a_delay += accu.latency
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xy_delay = Delay(2*widths.a, max(0, a_delay))
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z_delay = Delay(parallelism*widths.p, max(0, -a_delay))
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self.submodules += accu, xy_delay, z_delay, cordic
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self.latency = max(0, a_delay) + cordic[0].latency
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self.gain = cordic[0].gain
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self.comb += [
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self.a.ack.eq(1),
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self.f.ack.eq(1),
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self.p.ack.eq(1),
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q.o.ack.eq(1),
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xy_delay.i.eq(Cat(self.i.x, self.i.y)),
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z_delay.i.eq(Cat([zi[-widths.p:]
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for zi in accu.o.payload.flatten()])),
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eqh(accu.i.p, self.i.p),
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accu.i.f.eq(self.i.f),
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accu.i.clr.eq(self.i.clr),
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accu.i.stb.eq(self.i.stb),
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self.i.ack.eq(accu.i.ack),
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accu.o.ack.eq(1),
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[Cat(c.xi, c.yi).eq(xy_delay.o) for c in cordic],
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Cat([c.zi for c in cordic]).eq(z_delay.o),
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]
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c = []
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for i in range(parallelism):
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ci = Cordic(width=width, widthz=p_width,
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guard=None, eval_mode="pipelined")
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self.submodules += ci
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c.append(ci)
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qoi = getattr(q.o, "z{}".format(i))
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self.comb += [
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eqh(ci.xi, a),
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ci.yi.eq(0),
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eqh(ci.zi, qoi),
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eqh(self.o[i], ci.xo),
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]
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self.latency += c[0].latency
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self.gain = c[0].gain
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class DDSFast(Module):
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def __init__(self, width, t_width=None,
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a_width=None, p_width=None, f_width=None,
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a_order=4, p_order=1, f_order=2, parallelism=8):
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if t_width is None:
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t_width = width
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if a_width is None:
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a_width = width + (a_order - 1)*t_width
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if p_width is None:
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p_width = width + (p_order - 1)*t_width
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if f_width is None:
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f_width = width + (f_order + 1)*t_width
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a = Spline(order=a_order, width=a_width)
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p = Spline(order=p_order, width=p_width)
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f = Spline(order=f_order, width=f_width)
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self.submodules += a, p, f
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self.a = a.tri(t_width)
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self.f = f.tri(t_width)
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self.p = p.tri(t_width)
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self.i = [self.a, self.f, self.p]
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self.o = [[Signal((width, True)) for i in range(2)]
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for i in range(parallelism)]
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self.parallelism = parallelism
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self.latency = 0 # will be accumulated
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class SplineParallelDUC(ParallelDDS):
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def __init__(self, widths, orders, **kwargs):
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p = Spline(order=orders.p, width=widths.p)
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f = Spline(order=orders.f, width=widths.f)
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self.f = f.tri(widths.t)
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self.p = p.tri(widths.t)
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self.submodules += p, f
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self.ce = Signal(reset=1)
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self.clr = Signal()
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super().__init__(widths._replace(p=len(self.f.a0), f=len(self.f.a0)),
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**kwargs)
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self.latency += f.latency
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###
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self.latency += p.latency
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q = PhasedAccu(f_width, parallelism)
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self.submodules += q
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self.latency += q.latency
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da = [Signal((width, True)) for i in range(q.latency)]
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assert p.latency == f.latency
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self.sync += [
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If(q.i.stb & q.i.ack,
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eqh(da[0], a.o.a0),
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[da[i + 1].eq(da[i]) for i in range(len(da) - 1)],
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),
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If(p.o.stb & p.o.ack,
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q.i.clr.eq(0),
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),
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If(p.i.stb & p.i.ack,
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q.i.clr.eq(self.clr),
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),
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self.comb += [
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p.o.ack.eq(self.ce),
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f.o.ack.eq(self.ce),
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eqh(self.i.f, f.o.a0),
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eqh(self.i.p, p.o.a0),
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self.i.clr.eq(self.clr),
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self.i.stb.eq(p.o.stb & f.o.stb),
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]
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class SplineParallelDDS(SplineParallelDUC):
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def __init__(self, widths, orders, **kwargs):
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a = Spline(order=orders.a, width=widths.a)
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self.a = a.tri(widths.t)
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self.submodules += a
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super().__init__(widths._replace(a=len(self.a.a0)),
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orders, **kwargs)
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###
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self.comb += [
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a.o.ack.eq(self.ce),
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p.o.ack.eq(self.ce),
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f.o.ack.eq(self.ce),
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q.i.stb.eq(self.ce),
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eqh(q.i.p, p.o.a0),
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q.i.f.eq(f.o.a0),
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q.o.ack.eq(1),
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eqh(self.i.x, a.o.a0),
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self.i.y.eq(0),
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]
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c = []
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for i in range(parallelism):
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ci = Cordic(width=width, widthz=p_width,
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guard=None, eval_mode="pipelined")
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self.submodules += ci
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c.append(ci)
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qoi = getattr(q.o, "z{}".format(i))
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self.comb += [
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ci.xi.eq(da[-1]),
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ci.yi.eq(0),
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eqh(ci.zi, qoi),
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eqh(self.o[i][0], ci.xo),
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eqh(self.o[i][1], ci.yo),
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]
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self.latency += c[0].latency
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self.gain = c[0].gain
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class DDSSlow(Module):
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def __init__(self, width, t_width, a_width, p_width, f_width,
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a_order=4, p_order=1, f_order=2):
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a = Spline(order=a_order, width=a_width)
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p = Spline(order=p_order, width=p_width)
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f = Spline(order=f_order, width=f_width)
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self.submodules += a, p, f
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self.a = a.tri(t_width)
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self.f = f.tri(t_width)
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self.p = p.tri(t_width)
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self.i = [self.a, self.f, self.p]
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self.i_names = "a f p".split()
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self.o = [Signal((width, True)) for i in range(2)]
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self.ce = Signal()
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self.clr = Signal()
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self.latency = 0 # will be accumulated
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###
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self.latency += p.latency
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q = Accu(f_width)
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self.latency += q.latency
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da = CEInserter()(Delay)(width, q.latency)
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c = Cordic(width=width, widthz=p_width,
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guard=None, eval_mode="pipelined")
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self.latency += c.latency
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self.gain = c.gain
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self.submodules += q, da, c
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self.sync += [
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If(p.o.stb & p.o.ack,
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q.i.clr.eq(0),
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),
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If(p.i.stb & p.i.ack,
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q.i.clr.eq(self.clr),
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),
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]
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self.comb += [
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da.ce.eq(q.i.stb & q.i.ack),
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a.o.ack.eq(self.ce),
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p.o.ack.eq(self.ce),
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f.o.ack.eq(self.ce),
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q.i.stb.eq(self.ce),
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eqh(da.i, a.o.a0),
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eqh(q.i.p, p.o.a0),
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q.i.f.eq(f.o.a0),
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q.o.ack.eq(1),
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c.xi.eq(da.o),
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c.yi.eq(0),
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eqh(c.zi, q.o.z),
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eqh(self.o[0], c.xo),
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eqh(self.o[1], c.yo),
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]
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class DDS(Module):
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def __init__(self, width, t_width=None,
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a_width=None, p_width=None, f_width=None,
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a_order=4, p_order=1, f_order=2, parallelism=8):
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if t_width is None:
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t_width = width
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if a_width is None:
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a_width = width + (a_order - 1)*t_width
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if p_width is None:
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p_width = width + (p_order - 1)*t_width
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if f_width is None:
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f_width = width + (f_order + 1)*t_width
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self.b = [DDSSlow(width, t_width, a_width, p_width, f_width, a_order,
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p_order, f_order) for i in range(2)]
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p = Spline(order=1, width=p_width)
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f = Spline(order=1, width=f_width)
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self.submodules += self.b, p, f
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self.f0 = f.tri(t_width)
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self.p0 = p.tri(t_width)
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self.i = [self.f0, self.p0]
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self.i_names = "f0 p0".split()
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for i, bi in enumerate(self.b):
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self.i += bi.i
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for ii in bi.i_names:
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self.i_names.append("{}{}".format(ii, i + 1))
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for j in "afp":
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setattr(self, "{}{}".format(j, i + 1), getattr(bi, j))
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self.o = [[Signal((width, True)) for i in range(2)]
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for i in range(parallelism)]
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self.ce = Signal()
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self.clr = Signal()
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self.parallelism = parallelism
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self.latency = 0 # will be accumulated
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###
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self.latency += self.b[0].latency # TODO: f0/p0, q.latency delta
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q = PhasedAccu(f_width, parallelism)
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self.submodules += q
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self.sync += [
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If(p.o.stb & p.o.ack,
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q.i.clr.eq(0),
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),
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If(p.i.stb & p.i.ack,
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q.i.clr.eq(self.clr),
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),
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]
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self.comb += [
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[bi.ce.eq(self.ce) for bi in self.b],
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[bi.clr.eq(self.clr) for bi in self.b],
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p.o.ack.eq(self.ce),
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f.o.ack.eq(self.ce),
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q.i.stb.eq(self.ce),
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eqh(q.i.p, p.o.a0),
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eqh(q.i.f, f.o.a0),
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q.o.ack.eq(1),
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]
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x = self.sat_add(bi.o[0] for bi in self.b)
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y = self.sat_add(bi.o[1] for bi in self.b)
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c = []
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for i in range(parallelism):
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ci = Cordic(width=width, widthz=p_width,
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guard=None, eval_mode="pipelined")
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self.submodules += ci
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c.append(ci)
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qoi = getattr(q.o, "z{}".format(i))
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self.comb += [
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ci.xi.eq(x),
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ci.yi.eq(y),
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eqh(ci.zi, qoi),
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eqh(self.o[i][0], ci.xo),
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eqh(self.o[i][1], ci.yo),
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]
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self.latency += c[0].latency
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self.gain = self.b[0].gain * c[0].gain
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class Config(Module):
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def __init__(self):
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self.cfg = Record([("tap", 5), ("clr", 1), ("iq", 2)])
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self.i = Endpoint(self.cfg.layout)
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self.clr = Signal(4)
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self.iq_en = Signal(2)
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limit = [Signal((16, True)) for i in range(2*2)]
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self.limit = [limit[i:i + 2] for i in range(0, len(limit), 2)]
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self.i = Endpoint([("addr", bits_for(len(limit) + 2)), ("data", 16)])
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self.ce = Signal()
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###
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n = Signal(1 << len(self.i.tap))
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tap = Signal.like(self.i.tap)
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clk = Signal()
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clk0 = Signal()
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div = Signal(16)
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n = Signal.like(div)
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reg = Array([Cat(self.clr, self.iq_en), Cat(div, n)] + self.limit)
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self.comb += [
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self.i.ack.eq(1),
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clk.eq(Array(n)[tap]),
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self.ce.eq(n == 0),
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]
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self.sync += [
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clk0.eq(clk),
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self.ce.eq(0),
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If(clk0 ^ clk,
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self.ce.eq(1),
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n.eq(n - 1),
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If(self.ce,
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n.eq(div),
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),
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n.eq(n + 1),
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If(self.i.stb,
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n.eq(0),
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self.cfg.eq(self.i.payload),
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reg[self.i.addr].eq(self.i.data),
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),
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]
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class Channel(Module):
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def __init__(self, width=16, t_width=None, u_order=4, **kwargs):
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if t_width is None:
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t_width = width
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du = Spline(width=width + (u_order - 1)*t_width, order=u_order)
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da = DDS(width, t_width, **kwargs)
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class Channel(Module, SatAddMixin):
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def __init__(self, width=16, parallelism=4, widths=None, orders=None):
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if orders is None:
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orders = _Orders(a=4, f=2, p=1)
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if widths is None:
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widths = _Widths(t=width, a=orders.a*width, p=orders.p*width,
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f=3*width + (orders.f - 1)*width)
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cfg = Config()
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self.submodules += du, da, cfg
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self.i = [cfg.i, du.tri(t_width)] + da.i
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self.i_names = "cfg u".split() + da.i_names
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self.q_i = [Signal((width, True)) for i in range(da.parallelism)]
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self.q_o = [ai[1] for ai in da.o]
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self.o = [Signal((width, True)) for i in range(da.parallelism)]
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self.width = width
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self.parallelism = da.parallelism
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self.latency = da.latency + 1
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self.cordic_gain = da.gain
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a1 = SplineParallelDDS(widths, orders)
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a2 = SplineParallelDDS(widths, orders)
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b = SplineParallelDUC(widths, orders, parallelism=parallelism,
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a_delay=-a1.latency)
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u = Spline(width=widths.a, order=orders.a)
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du = Delay(widths.a, a1.latency + b.latency - u.latency)
|
||||
self.submodules += cfg, a1, a2, b, u, du
|
||||
self.cfg = cfg.i
|
||||
self.u = u.tri(widths.t)
|
||||
self.i = [self.cfg, self.u, a1.a, a1.f, a1.p, a2.a, a2.f, a2.p, b.f, b.p]
|
||||
self.y_in = [Signal((width, True)) for i in range(b.parallelism)]
|
||||
self.y_out = b.yo
|
||||
self.o = [Signal((width, True)) for i in range(b.parallelism)]
|
||||
self.widths = widths
|
||||
self.orders = orders
|
||||
self.parallelism = parallelism
|
||||
self.latency = a1.latency + b.latency + 1
|
||||
self.cordic_gain = a1.gain*b.gain
|
||||
|
||||
###
|
||||
|
||||
# delay du to match da
|
||||
ddu = Delay((width, True), da.latency - du.latency)
|
||||
self.submodules += ddu
|
||||
self.comb += [
|
||||
ddu.i.eq(du.o.a0[-width:]),
|
||||
da.clr.eq(cfg.cfg.clr),
|
||||
da.ce.eq(cfg.ce),
|
||||
du.o.ack.eq(cfg.ce),
|
||||
a1.ce.eq(cfg.ce),
|
||||
a2.ce.eq(cfg.ce),
|
||||
b.ce.eq(cfg.ce),
|
||||
u.o.ack.eq(cfg.ce),
|
||||
Cat(a1.clr, a2.clr, b.clr).eq(cfg.clr),
|
||||
b.i.x.eq(self.sat_add([a1.xo[0], a2.xo[0]])),
|
||||
b.i.y.eq(self.sat_add([a1.yo[0], a2.yo[0]])),
|
||||
eqh(du.i, u.o.a0),
|
||||
]
|
||||
# wire up outputs and q_{i,o} exchange
|
||||
for oi, ai, qi in zip(self.o, da.o, self.q_i):
|
||||
for o, x, y in zip(self.o, b.xo, self.y_in):
|
||||
self.sync += [
|
||||
oi.eq(self.sat_add([
|
||||
ddu.o +
|
||||
# du.o.a0[-width:],
|
||||
Mux(cfg.cfg.iq[0], ai[0], 0),
|
||||
Mux(cfg.cfg.iq[1], qi, 0)])),
|
||||
o.eq(self.sat_add([du.o,
|
||||
Mux(cfg.iq_en[0], x, 0),
|
||||
Mux(cfg.iq_en[1], y, 0)])),
|
||||
]
|
||||
|
||||
def connect_q(self, buddy):
|
||||
for i, qi in enumerate(self.q_i):
|
||||
self.comb += qi.eq(buddy.q_o[i])
|
||||
def connect_q_from(self, buddy):
|
||||
self.comb += Cat(self.y_in).eq(Cat(buddy.y_out))
|
||||
|
|
|
|||
Loading…
Reference in New Issue