mirror of https://github.com/m-labs/artiq.git
drtio: add infrastructure for reporting busy/collision errors
This commit is contained in:
parent
0a687b7902
commit
008678b741
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@ -20,6 +20,12 @@ use proto::*;
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pub enum Packet {
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EchoRequest,
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EchoReply,
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RtioErrorRequest,
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RtioNoErrorReply,
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RtioErrorCollisionReply,
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RtioErrorBusyReply,
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MonitorRequest { channel: u16, probe: u8 },
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MonitorReply { value: u32 },
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InjectionRequest { channel: u16, overrd: u8, value: u8 },
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@ -30,25 +36,31 @@ pub enum Packet {
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impl Packet {
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pub fn read_from(reader: &mut Read) -> io::Result<Packet> {
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Ok(match read_u8(reader)? {
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0 => Packet::EchoRequest,
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1 => Packet::EchoReply,
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2 => Packet::MonitorRequest {
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0x00 => Packet::EchoRequest,
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0x01 => Packet::EchoReply,
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0x20 => Packet::RtioErrorRequest,
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0x21 => Packet::RtioNoErrorReply,
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0x22 => Packet::RtioErrorCollisionReply,
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0x23 => Packet::RtioErrorBusyReply,
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0x40 => Packet::MonitorRequest {
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channel: read_u16(reader)?,
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probe: read_u8(reader)?
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},
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3 => Packet::MonitorReply {
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0x41 => Packet::MonitorReply {
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value: read_u32(reader)?
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},
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4 => Packet::InjectionRequest {
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0x50 => Packet::InjectionRequest {
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channel: read_u16(reader)?,
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overrd: read_u8(reader)?,
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value: read_u8(reader)?
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},
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5 => Packet::InjectionStatusRequest {
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0x51 => Packet::InjectionStatusRequest {
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channel: read_u16(reader)?,
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overrd: read_u8(reader)?
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},
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6 => Packet::InjectionStatusReply {
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0x52 => Packet::InjectionStatusReply {
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value: read_u8(reader)?
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},
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_ => return Err(io::Error::new(io::ErrorKind::InvalidData, "unknown packet type"))
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@ -57,30 +69,36 @@ impl Packet {
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pub fn write_to(&self, writer: &mut Write) -> io::Result<()> {
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match *self {
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Packet::EchoRequest => write_u8(writer, 0)?,
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Packet::EchoReply => write_u8(writer, 1)?,
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Packet::EchoRequest => write_u8(writer, 0x00)?,
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Packet::EchoReply => write_u8(writer, 0x01)?,
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Packet::RtioErrorRequest => write_u8(writer, 0x20)?,
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Packet::RtioNoErrorReply => write_u8(writer, 0x21)?,
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Packet::RtioErrorCollisionReply => write_u8(writer, 0x22)?,
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Packet::RtioErrorBusyReply => write_u8(writer, 0x23)?,
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Packet::MonitorRequest { channel, probe } => {
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write_u8(writer, 2)?;
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write_u8(writer, 0x40)?;
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write_u16(writer, channel)?;
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write_u8(writer, probe)?;
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},
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Packet::MonitorReply { value } => {
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write_u8(writer, 3)?;
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write_u8(writer, 0x41)?;
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write_u32(writer, value)?;
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},
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Packet::InjectionRequest { channel, overrd, value } => {
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write_u8(writer, 4)?;
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write_u8(writer, 0x50)?;
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write_u16(writer, channel)?;
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write_u8(writer, overrd)?;
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write_u8(writer, value)?;
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},
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Packet::InjectionStatusRequest { channel, overrd } => {
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write_u8(writer, 5)?;
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write_u8(writer, 0x51)?;
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write_u16(writer, channel)?;
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write_u8(writer, overrd)?;
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},
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Packet::InjectionStatusReply { value } => {
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write_u8(writer, 6)?;
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write_u8(writer, 0x52)?;
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write_u8(writer, value)?;
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}
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}
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@ -161,6 +179,18 @@ pub mod hw {
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}
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}
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pub fn recv_timeout(timeout_ms: u64) -> io::Result<Packet> {
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let limit = board::clock::get_ms() + timeout_ms;
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while board::clock::get_ms() < limit {
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match recv() {
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Ok(None) => (),
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Ok(Some(packet)) => return Ok(packet),
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Err(e) => return Err(e)
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}
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}
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return Err(io::Error::new(io::ErrorKind::TimedOut, "timed out waiting for data"))
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}
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fn tx_get_buffer() -> &'static mut [u8] {
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unsafe {
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while board::csr::drtio::aux_tx_read() != 0 {}
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@ -35,32 +35,22 @@ fn read_probe_local(channel: u16, probe: u8) -> u32 {
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}
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#[cfg(has_drtio)]
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fn read_probe_drtio(io: &Io, channel: u16, probe: u8) -> u32 {
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fn read_probe_drtio(channel: u16, probe: u8) -> u32 {
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if rtio_mgt::drtio::link_is_running() {
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let request = drtioaux::Packet::MonitorRequest { channel: channel, probe: probe };
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drtioaux::hw::send(&request).unwrap();
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let timeout = clock::get_ms() + 20;
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while clock::get_ms() < timeout {
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if !rtio_mgt::drtio::link_is_running() {
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return 0
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}
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match drtioaux::hw::recv() {
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Ok(None) => (),
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Ok(Some(drtioaux::Packet::MonitorReply { value })) => return value,
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Ok(Some(_)) => warn!("received unexpected aux packet"),
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Err(e) => warn!("aux packet error ({})", e)
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}
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io.relinquish().unwrap();
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match drtioaux::hw::recv_timeout(10) {
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Ok(drtioaux::Packet::MonitorReply { value }) => return value,
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Ok(_) => error!("received unexpected aux packet"),
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Err(e) => error!("aux packet error ({})", e)
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}
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warn!("aux packet timeout");
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0
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} else {
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0
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}
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}
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fn read_probe(_io: &Io, channel: u32, probe: u8) -> u32 {
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fn read_probe(channel: u32, probe: u8) -> u32 {
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#[cfg(has_rtio_moninj)]
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{
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if channel & 0xff0000 == 0 {
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@ -70,7 +60,7 @@ fn read_probe(_io: &Io, channel: u32, probe: u8) -> u32 {
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#[cfg(has_drtio)]
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{
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if channel & 0xff0000 != 0 {
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return read_probe_drtio(_io, channel as u16, probe)
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return read_probe_drtio(channel as u16, probe)
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}
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}
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error!("read_probe: unrecognized channel number {}", channel);
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@ -126,35 +116,25 @@ fn read_injection_status_local(channel: u16, overrd: u8) -> u8 {
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}
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#[cfg(has_drtio)]
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fn read_injection_status_drtio(io: &Io, channel: u16, overrd: u8) -> u8 {
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fn read_injection_status_drtio(channel: u16, overrd: u8) -> u8 {
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if rtio_mgt::drtio::link_is_running() {
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let request = drtioaux::Packet::InjectionStatusRequest {
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channel: channel,
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overrd: overrd
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};
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drtioaux::hw::send(&request).unwrap();
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let timeout = clock::get_ms() + 20;
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while clock::get_ms() < timeout {
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if !rtio_mgt::drtio::link_is_running() {
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return 0
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}
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match drtioaux::hw::recv() {
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Ok(None) => (),
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Ok(Some(drtioaux::Packet::InjectionStatusReply { value })) => return value,
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Ok(Some(_)) => warn!("received unexpected aux packet"),
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Err(e) => warn!("aux packet error ({})", e)
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}
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io.relinquish().unwrap();
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match drtioaux::hw::recv_timeout(10) {
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Ok(drtioaux::Packet::InjectionStatusReply { value }) => return value,
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Ok(_) => error!("received unexpected aux packet"),
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Err(e) => error!("aux packet error ({})", e)
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}
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warn!("aux packet timeout");
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0
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} else {
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0
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}
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}
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fn read_injection_status(_io: &Io, channel: u32, probe: u8) -> u8 {
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fn read_injection_status(channel: u32, probe: u8) -> u8 {
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#[cfg(has_rtio_moninj)]
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{
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if channel & 0xff0000 == 0 {
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@ -164,7 +144,7 @@ fn read_injection_status(_io: &Io, channel: u32, probe: u8) -> u8 {
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#[cfg(has_drtio)]
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{
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if channel & 0xff0000 != 0 {
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return read_injection_status_drtio(_io, channel as u16, probe)
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return read_injection_status_drtio(channel as u16, probe)
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}
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}
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error!("read_injection_status: unrecognized channel number {}", channel);
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@ -191,7 +171,7 @@ fn connection_worker(io: &Io, mut stream: &mut TcpStream) -> io::Result<()> {
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},
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HostMessage::Inject { channel, overrd, value } => inject(channel, overrd, value),
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HostMessage::GetInjectionStatus { channel, overrd } => {
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let value = read_injection_status(io, channel, overrd);
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let value = read_injection_status(channel, overrd);
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let reply = DeviceMessage::InjectionStatus {
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channel: channel,
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overrd: overrd,
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@ -206,7 +186,7 @@ fn connection_worker(io: &Io, mut stream: &mut TcpStream) -> io::Result<()> {
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if clock::get_ms() > next_check {
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for (&(channel, probe), previous) in watch_list.iter_mut() {
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let current = read_probe(io, channel, probe);
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let current = read_probe(channel, probe);
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if previous.is_none() || (previous.unwrap() != current) {
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let message = DeviceMessage::MonitorStatus {
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channel: channel,
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@ -43,7 +43,8 @@ pub mod drtio {
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pub fn startup(io: &Io) {
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io.spawn(4096, link_thread);
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io.spawn(4096, error_thread);
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io.spawn(4096, local_error_thread);
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io.spawn(4096, aux_error_thread);
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}
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static mut LINK_RUNNING: bool = false;
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@ -144,7 +145,7 @@ pub mod drtio {
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}
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}
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pub fn error_thread(io: Io) {
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pub fn local_error_thread(io: Io) {
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loop {
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unsafe {
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io.until(|| csr::drtio::protocol_error_read() != 0).unwrap();
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@ -162,6 +163,22 @@ pub mod drtio {
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}
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}
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}
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pub fn aux_error_thread(io: Io) {
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loop {
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io.sleep(200).unwrap();
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if link_is_running() {
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drtioaux::hw::send(&drtioaux::Packet::RtioErrorRequest).unwrap();
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match drtioaux::hw::recv_timeout(10) {
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Ok(drtioaux::Packet::RtioNoErrorReply) => (),
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Ok(drtioaux::Packet::RtioErrorCollisionReply) => error!("RTIO collision (in satellite)"),
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Ok(drtioaux::Packet::RtioErrorBusyReply) => error!("RTIO busy (in satellite)"),
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Ok(_) => error!("received unexpected aux packet"),
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Err(e) => error!("aux packet error ({})", e)
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}
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}
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}
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}
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}
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#[cfg(not(has_drtio))]
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@ -16,6 +16,27 @@ fn process_aux_packet(p: &drtioaux::Packet) {
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// and u16 otherwise; hence the `as _` conversion.
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match *p {
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drtioaux::Packet::EchoRequest => drtioaux::hw::send(&drtioaux::Packet::EchoReply).unwrap(),
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drtioaux::Packet::RtioErrorRequest => {
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let errors;
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unsafe {
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errors = board::csr::drtio::rtio_error_read();
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}
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if errors & 1 != 0 {
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unsafe {
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board::csr::drtio::rtio_error_write(1);
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}
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drtioaux::hw::send(&drtioaux::Packet::RtioErrorCollisionReply).unwrap();
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} else if errors & 2 != 0 {
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unsafe {
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board::csr::drtio::rtio_error_write(2);
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}
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drtioaux::hw::send(&drtioaux::Packet::RtioErrorBusyReply).unwrap();
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} else {
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drtioaux::hw::send(&drtioaux::Packet::RtioNoErrorReply).unwrap();
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}
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}
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drtioaux::Packet::MonitorRequest { channel, probe } => {
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let value;
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#[cfg(has_rtio_moninj)]
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@ -8,29 +8,28 @@ from misoc.interconnect.csr import *
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class RTErrorsSatellite(Module, AutoCSR):
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def __init__(self, rt_packet, ios):
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self.protocol_error = CSR(4)
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self.rtio_error = CSR(2)
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def error_csr(csr, *sources):
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for n, source in enumerate(sources):
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pending = Signal(related=source)
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ps = PulseSynchronizer("rtio", "sys")
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self.submodules += ps
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self.comb += ps.i.eq(source)
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self.sync += [
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If(csr.re & csr.r[n], pending.eq(0)),
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If(ps.o, pending.eq(1))
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]
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self.comb += csr.w[n].eq(pending)
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# The master is normally responsible for avoiding output overflows and
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# output underflows.
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# Error reports here are only for diagnosing internal ARTIQ bugs.
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unknown_packet_type = Signal()
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packet_truncated = Signal()
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write_overflow = Signal()
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write_underflow = Signal()
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self.comb += self.protocol_error.w.eq(
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Cat(unknown_packet_type, packet_truncated,
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write_underflow, write_overflow))
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for n, (target, source) in enumerate([
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(unknown_packet_type, rt_packet.unknown_packet_type),
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(packet_truncated, rt_packet.packet_truncated),
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(write_underflow, ios.write_underflow),
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(write_overflow, ios.write_overflow)]):
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ps = PulseSynchronizer("rtio", "sys")
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self.submodules += ps
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self.comb += ps.i.eq(source)
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self.sync += [
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If(self.protocol_error.re & self.protocol_error.r[n], target.eq(0)),
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If(ps.o, target.eq(1))
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]
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error_csr(self.protocol_error,
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rt_packet.unknown_packet_type,
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rt_packet.packet_truncated,
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ios.write_underflow,
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ios.write_overflow)
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error_csr(self.rtio_error,
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ios.collision,
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ios.busy)
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@ -11,6 +11,8 @@ class IOS(Module):
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def __init__(self, rt_packet, channels, max_fine_ts_width, full_ts_width):
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self.write_underflow = Signal()
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self.write_overflow = Signal()
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self.collision = Signal()
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self.busy = Signal()
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self.rt_packet = rt_packet
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self.max_fine_ts_width = max_fine_ts_width
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@ -26,7 +28,9 @@ class IOS(Module):
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self.sync.rio += [
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self.write_underflow.eq(0),
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self.write_overflow.eq(0)
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self.write_overflow.eq(0),
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self.collision.eq(0),
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self.busy.eq(0)
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]
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for n, channel in enumerate(channels):
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self.add_output(n, channel)
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